2024年4月16日发(作者：台积电市值)
元器件交易网
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14517B
Dual 64-Bit Static Shift Register
The MC14517B dual 64–bit static shift register consists of two identical,
independent, 64–bit registers. Each register has separate clock and write
enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data
input is entered by clocking, regardless of the state of the write enable input.
An output is disabled (open circuited) when the write enable input is high.
During this time, data appearing at the data input as well as the 16–bit,
32–bit, and 48–bit taps may be entered into the device by application of a
clock pulse. This feature permits the register to be loaded with 64 bits in 16
clock periods, and also permits bus logic to be used. This device is useful in
time delay circuits, temporary memory storage circuits, and other serial shift
register applications.
•
•
•
•
•
•
•
•
Diode Protection on All Inputs
Fully Static Operation
Output Transitions Occur on the Rising Edge of the Clock Pulse
Exceedingly Slow Input Transition Rates May Be Applied to the Clock
Input
3–State Output at 64th–Bit Allows Use in Bus Logic Applications
Shift Registers of any Length may be Fully Loaded with 16 Clock Pulses
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
L
Parameter
DC Supply Voltage
Input or Output Voltage (DC or Transient)
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package†
Storage Temperature
Value
– 0.5 to + 18.0
– 0.5 to V
DD
+ 0.5
± 10
500
Unit
V
V
mA
mW
_C
_C
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
T
A
= – 55° to 125°C for all packages.
MAXIMUM RATINGS
(Voltages referenced to V
SS
)
PIN ASSIGNMENT
Q16
A
Q48
A
WE
A
C
A
Q64
A
Q32
A
D
A
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
Q16
B
Q48
B
WE
B
C
B
Q64
B
Q32
B
D
B
T
stg
– 65 to + 150
260Lead Temperature (8–Second Soldering)
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
FUNCTIONAL TRUTH TABLE
(X = Don’t Care)
Clock
0
0
1
1
Write
Enable
0
1
0
1
0
1
0
1
Data
X
X
X
X
Data entered
into 1st Bit
Data entered
into 1st Bit
X
X
16–Bit Tap
Content of 16–Bit
Displayed
High Impedance
Content of 16–Bit
Displayed
High Impedance
Content of 16–Bit
Displayed
Data at tap
entered into 17–Bit
Content of 16–Bit
Displayed
High Impedance
32–Bit Tap
Content of 32–Bit
Displayed
High Impedance
Content of 32–Bit
Displayed
High Impedance
Content of 32–Bit
Displayed
Data at tap
entered into 33–Bit
Content of 32–Bit
Displayed
High Impedance
48–Bit Tap
Content of 48–Bit
Displayed
High Impedance
Content of 48–Bit
Displayed
High Impedance
Content of 48–Bit
Displayed
Data at tap
entered into 49–Bit
Content of 48–Bit
Displayed
High Impedance
64–Bit Tap
Content of 64–Bit
Displayed
High Impedance
Content of 64–Bit
Displayed
High Impedance
Content of 64–Bit
Displayed
High Impedance
Content of 64–Bit
Displayed
High Impedance
REV 3
1/94
©
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
MC14517B
403
元器件交易网
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
Characteristic
Output Voltage
V
in
= V
DD
or 0
“0” Level
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
5.0
10
15
5.0
10
15
15
—
5.0
10
15
5.0
10
15
Min
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 3.0
– 0.64
– 1.6
– 4.2
0.64
1.6
4.2
—
—
—
—
—
– 55_C
Max
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
± 0.1
—
5.0
10
20
Min
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 2.4
– 0.51
– 1.3
– 3.4
0.51
1.3
3.4
—
—
—
—
—
25_C
Typ #
0
0
0
5.0
10
15
2.25
4.50
6.75
2.75
5.50
8.25
– 4.2
– 0.88
– 2.25
– 8.8
0.88
2.25
8.8
±0.00001
5.0
0.005
0.010
0.015
Max
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
± 0.1
7.5
5.0
10
20
125_C
Min
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 1.7
– 0.36
– 0.9
– 2.4
0.36
0.9
2.4
—
—
—
—
—
Max
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
Vdc
—
—
—
mAdc
—
—
—
—
—
—
—
± 1.0
—
150
300
600
mAdc
Unit
Vdc
“1” Level
V
in
= 0 or V
DD
Input Voltage“0” Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
Three–State Leakage Current
Source
V
OH
Vdc
V
IL
Vdc
V
IH
I
OH
SinkI
OL
I
in
C
in
I
DD
µAdc
pF
µAdc
I
T
I
T
= (4.2 µA/kHz) f + I
DD
I
T
= (8.8 µA/kHz) f + I
DD
I
T
= (13.7 µA/kHz) f + I
DD
µAdc
I
TL
15—± 0.1—± 0.0001± 0.1—± 3.0µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**āThe formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk
where: I
T
is in µA (per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.004.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, V
in
and V
out
should be constrained to the range V
SS
≤ (V
in
or V
out
) ≤ V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V
SS
or V
DD
). Unused outputs must
be left open.
MC14517B
404
MOTOROLA CMOS LOGIC DATA
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