2024年5月17日发(作者：怎么看自己电脑的配置和具体型号)

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HD74LS273

Octal D-type Positive-edge-triggered Flip-Flops (with Clear)

REJ03D0473–0300

Rev.3.00

Jul.15.2005

The HD74LS273, positive-edge-triggered flip-flops utilize LS TTL circuitry to implement D-type flip-flop logic with a

direct clear input.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going

edge of the clock pulse.

When the clock input is at either the high or low level, the D input signal has no effect at the output.

Features

• Ordering Information

Part Name Package Type

Package Code

(Previous Code)

PRDP0020AC-B

(DP-20NEV)

PRSP0020DD-B

(FP-20DAV)

Package

Abbreviation

Taping Abbreviation

(Quantity)

HD74LS273P DILP-20 pin

HD74LS273FPEL SOP-20 pin (JEITA)

HD74LS273RPEL SOP-20 pin (JEDEC)

P —

FP EL (2,000 pcs/reel)

EL (1,000 pcs/reel)

PRSP0020DC-A

RP

(FP-20DBV)

Note: Please consult the sales office for the above package availability.

Pin Arrangement

Clear

1Q

1D

2D

2Q

3Q

3D

4D

4Q

GND

1

2

3

4

5

6

7

8

9

10

Q

Clear

DCK

D

Q

Q

CK

Clear

Q

Clear

CKD

CKD

Clear

Q

Q

Clear

CKD

CKD

Clear

Q

20

19

18

17

16

15

14

13

12

11

V

CC

8Q

8D

7D

7Q

6Q

6D

5D

5Q

Clock

Clear

DCK

DCK

Clear

Q

(Top view)

Rev.3.00, Jul.15.2005, page 1 of 6

元器件交易网

HD74LS273

Function Table

Inputs Output

Clear Clock D Q

L X X L

H ↑ H H

H ↑ L L

H L X Q

0

Notes: H; high level, L; low level, X; irrelevant

↑; transition from low to high level

Q

0

; level of Q before the indicated steady-state input conditions were established.

Block Diagram

1D2D3D4D5D6D7D8D

Clock (1)

D

Q

CK

Clear

D

Q

CK

Clear

D

Q

CK

Clear

D

Q

CK

Clear

D

Q

CK

Clear

D

Q

CK

Clear

D

Q

CK

Clear

D

Q

CK

Clear

Clear (2)

1Q2Q3Q4Q5Q6Q7Q8Q

Absolute Maximum Ratings

Supply voltage

Input voltage

Power dissipation

Storage temperature

Item Symbol Ratings Unit

V

CC

7 V

V

IN

7 V

Tstg –65 to +150 °C

P

T

400 mW

Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.

Recommended Operating Conditions

Supply voltage

Output current

V

CC

4.75 5.00 5.25 V

I

OH

— — –400 µA

I

OL

— — 8 mA

ƒ

clock

0 — 30 MHz

t

w (clock)

20 — —

t

w (clear)

20 — —

ns

ns

Item Symbol Min Typ Max Unit

Operating temperature Topr –20 25 75 °C

Clock frequency

Clock pulse width

Clear pulse width

Data setup time

Clear (inactive-state) setup time

Data hold time

t

su (data)

20↑ — — ns

t

su (clear)

25↑ — — ns

t

h (data)

5↑ — — ns

Rev.3.00, Jul.15.2005, page 2 of 6

元器件交易网

HD74LS273

Electrical Characteristics

(Ta = –20 to +75 °C)

Item Symbol min. typ.* max. Unit

V

IH

2.0 — — V

Input voltage

V

IL

— — 0.8 V

Condition

Output voltage

Input current

Short-circuit output current

Supply current

Input clamp voltage

Notes: * V

CC

= 5 V, Ta = 25°C

** With all outputs open and 4.5 V applied to all data and clear inputs, I

CC

is measured after a momentary

ground, then 4.5 V is applied to clock.

V

CC

= 4.75 V, V

IH

= 2 V, V

IL

= 0.8 V,

V

OH

2.7 — — V

I

OH

= –400 µA

— — 0.5 I

OL

= 8 mA

V

CC

= 4.75 V, V

IH

= 2 V,

V

OL

V

— — 0.4 I

OL

= 4 mA

V

IL

= 0.8 V

I

IH

— 20 µA V

CC

= 5.25 V, V

I

= 2.7 V

I

IL

— –0.4 mA V

CC

= 5.25 V, V

I

= 0.4 V

0.1 mA V

CC

= 5.25 V, V

I

= 7 V I

I

—

I

OS

–20 — –100 mA V

CC

= 5.25 V

I

CC

** — 17 27 mA V

CC

= 5.25 V

V

IK

— — –1.5 V V

CC

= 4.75 V, I

IN

= –18 mA

Switching Characteristics

(V

CC

= 5 V, Ta = 25°C)

Item Symbol Inputs min. typ. max. Unit Condition

Maximum clock frequency ƒ

max

Clock 30 40 — MHz

t

PHL

Clear — 18 27

C

L

= 15 pF, R

L

= 2 kΩ

ns

Propagation delay time

t

PLH

— 17 27

Clock

— 18 27 t

PHL

Testing Method

Test Circuit

V

CC

Input

4.5V

P.G.

Z

out

= 50Ω

Input

P.G.

Z

out

= 50Ω

D

Clock

Clear

Output

Q

R

L

C

L

Notes: 1. C

L

includes probe and jig capacitance.

2. All diodes are 1S2074(H).

Rev.3.00, Jul.15.2005, page 3 of 6

元器件交易网

HD74LS273

Waveforms 1

t

TLH

90%

1.3 V

10%

90%

1.3 V

10%

t

THL

3V

1.3 V

Data

0V

t

h

3V

t

su

t

TLH

Clock

t

h

t

THL

90%90%

1.3 V1.3 V

10%

t

su

10%

1.3 V

0V

t

w

t

PHL

V

OH

t

w

t

PLH

Q

1.3 V1.3 V

V

OL

Notes: Input pulse; t

TLH

≤ 15 ns, t

THL

≤ 6 ns,

Clock input; PRR = 1 MHz, duty cycle 50%

Data input; PRR = 500 kHz, duty cycle 50%

Waveforms 2

t

THL

Clear

90%

1.3V

t

TLH

90%

1.3V

10%

t

w

t

THL

Clock

t

PHL

t

w

Q

1.3V

t

PLH

1.3V

V

OL

90%

1.3V

10%

t

TLH

90%

1.3V

10%

3V

0V

V

OH

3V

0V

10%

t

w

Note: Input pulse: t

TLH

≤ 15 ns, t

THL

≤ 6 ns, PRR = 1 MHz.

Rev.3.00, Jul.15.2005, page 4 of 6

元器件交易网

HD74LS273

Package Dimensions

JEITA Package Code

P-DIP20-6.3x24.5-2.54

RENESAS Code

PRDP0020AC-B

Previous Code

DP-20NEV

MASS[Typ.]

1.26g

D

2011

1

0.89

b

3

10

Z

E

Reference

Symbol

Dimension in Millimeters

MinNom

7.62

24.50

6.30

25.40

7.00

5.08

0.51

0.400.48

1.30

0.19

0

°

2.292.54

0.250.31

15

°

2.79

1.27

2.54

0.56

Max

A

A

1

e

D

E

L

1

A

A

1

b

p

3

e

b

p

θ

e

1

c

b

c

θ

e

Z

( Ni/Pd/Au plating )

L

JEITA Package Code

P-SOP20-5.5x12.6-1.27

RENESAS Code

PRSP0020DD-B

Previous Code

FP-20DAV

MASS[Typ.]

0.31g

*1

D

11

F

NOTE)

1. DIMENSIONS"*1 (Nom)"AND"*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION"*3"DOES NOT

INCLUDE TRIM OFFSET.

20

b

p

E

H

E

Index mark

Reference

Symbol

*

2

c

Dimension in Millimeters

MinNom

12.60

5.50

Max

13.0

Terminal cross section

( Ni/Pd/Au plating )

1

Z

e

*3

D

E

A

2

A

1

0.00

10

b

p

xM

L

1

0.100.20

2.20A

b

p

b

1

c

c

1

0.340.40

0.46

0.150.200.25

A

θ

H

E

0

°

7.50

7.80

1.27

8

°

8.00

θ

A

1

y

L

e

x

y

0.12

0.15

0.80

0.50

1

Detail F

Z

L

L

0.70

1.15

0.90

Rev.3.00, Jul.15.2005, page 5 of 6

元器件交易网

HD74LS273

JEITA Package Code

P-SOP20-7.5x12.8-1.27

RENESAS Code

PRSP0020DC-A

Previous Code

FP-20DBV

MASS[Typ.]

0.52g

*1

D

11

F

NOTE)

1. DIMENSIONS"*1 (Nom)"AND"*2"

@ DO NOT INCLUDE MOLD FLASH.

2. DIMENSION"*3"DOES NOT

@ INCLUDE TRIM OFFSET.

20

b

p

*

2

H

E

E

Index mark

Reference

Symbol

c

Dimension in Millimeters

MinNom

12.80

7.50

Max

13.2

Terminal cross section

( Ni/Pd/Au plating )

1

Z

e

*3

D

E

A

2

10

b

p

xM

L

1

A

1

A

b

p

b

1

c

c

1

0.100.200.30

2.65

0.340.40

0.46

0.200.250.30

A

θ

H

E

e

0

°

10.00

10.40

1.27

8

°

10.65

θ

A

1

y

L

x

y

Z

0.12

0.15

0.935

0.40

1

Detail F

L

L

0.70

1.45

1.27

Rev.3.00, Jul.15.2005, page 6 of 6

元器件交易网

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