I am trying automatically generate Verilog from VLSI stick diagrams for logical output validation. The problem I am running into is that in general, transistors in VLSI are symmetrical, but the Verilog switch-level primitives each have a problem.

• nmos/pmos: Strictly unidirectional; source and drain are fixed. In reality, source and drain can change sides depending on the circuit state; the body is not connected to the source. See the example circuit below, in which the source and drain of transistor C depend on the states of A and B.
• tranif1/tranif0: Activation only depends on the gate, but it should depend on the source as well (nmos should only transfer 0 and pmos should only transfer 1).

So I need to combine the bidirectional feature of tranif0/tranif1 with the source dependency of nmos/pmos.

Does anyone have any suggestions for a workaround that accomplishes this without causing issues? It needs to be generally applicable since this is for automatic code generation. The Verilog does not need to exactly represent the topology of the diagram as long as it correctly produces its output. I'm not interested in analog effects, voltage drop, etc - this is a purely logic-level simulation.

I am trying automatically generate Verilog from VLSI stick diagrams for logical output validation. The problem I am running into is that in general, transistors in VLSI are symmetrical, but the Verilog switch-level primitives each have a problem.

• nmos/pmos: Strictly unidirectional; source and drain are fixed. In reality, source and drain can change sides depending on the circuit state; the body is not connected to the source. See the example circuit below, in which the source and drain of transistor C depend on the states of A and B.
• tranif1/tranif0: Activation only depends on the gate, but it should depend on the source as well (nmos should only transfer 0 and pmos should only transfer 1).

So I need to combine the bidirectional feature of tranif0/tranif1 with the source dependency of nmos/pmos.

Does anyone have any suggestions for a workaround that accomplishes this without causing issues? It needs to be generally applicable since this is for automatic code generation. The Verilog does not need to exactly represent the topology of the diagram as long as it correctly produces its output. I'm not interested in analog effects, voltage drop, etc - this is a purely logic-level simulation.

• verilog
• simulation
• vlsi

Share Improve this question Follow asked Feb 3 at 2:29 Nick O.Nick O. 18511 silver badge77 bronze badges

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2 Answers 2

Sorted by: Reset to default 1

A solution I've seen is converting MOS primitives directly connected to VSS/VDD as unidirectional nmos/pmos gates and the rest as tran gates. There may be more nuances using unidirectional gates when directly connected to other non-mos primitives like a buf gate.

I've come to the following solution for now, but I doubt I've covered all the edge cases. It just passes the few tests I've run so far. Handling "x" in a way that propagates well will probably be a challenge.

module ideal_nmos(
    inout wire t1,
    inout wire t2,
    input wire gate
);

    wire gate_active;
    assign gate_active = (gate === 1'b1) ? 1'b1 : 1'b0;
    assign t1 = (gate_active && (t2 === 1'b0)) ? 1'b0 : 1'bz;
    assign t2 = (gate_active && (t1 === 1'b0)) ? 1'b0 : 1'bz;
endmodule

module ideal_pmos(
    inout wire t1,
    inout wire t2,
    input wire gate
);

    wire gate_active;
    assign gate_active = (gate === 1'b0) ? 1'b1 : 1'b0;
    assign t1 = (gate_active && (t2 === 1'b1)) ? 1'b1 : 1'bz;
    assign t2 = (gate_active && (t1 === 1'b1)) ? 1'b1 : 1'bz;
endmodule