In Performance optimization, and how to do it wrong the author claims:

1. the CPU can't predict more than one branch per cycle

2. A single if statement inside a loop is enough to stop any further instructions from being decoded in that cycle.

1 contradicts measurements by uops.info for jz and jnz which show a reciprocal throughput of 0.50. Are there are different port limits for taken vs not taken branches like Haswell/Skylake?

2 is not mentioned in the Software Optimization Guide for the AMD Zen4 Microarchitecture. The only similar note is in 2.9 Instruction Fetch and Decode, but jcc is only 6 bytes in length. Do the decoders stop after decoding a branch?

Only the first decode slot (of four) can decode instructions greater than 10 bytes in length. Avoid having more than one instruction in a sequence of four that is greater than 10 bytes in length.

Are these performance limits for Zen 4 documented anywhere?