I was reading the lecture notes here about Demand Paging. The author states that:

• Restarting process execution after a page fault is tricky, since the fault may have occurred in the middle of an instruction.
  • If instructions are idempotent, just restart the faulting instruction (hardware saves instruction address during page fault).

How does idempotence, specifically instruction idempotence, make restarting the instruction easy? How is idempotence related in restarting instructions?

I was reading the lecture notes here about Demand Paging. The author states that:

• Restarting process execution after a page fault is tricky, since the fault may have occurred in the middle of an instruction.
  • If instructions are idempotent, just restart the faulting instruction (hardware saves instruction address during page fault).

How does idempotence, specifically instruction idempotence, make restarting the instruction easy? How is idempotence related in restarting instructions?

• x86
• operating-system
• cpu-architecture
• paging
• idempotent

Share Improve this question Follow edited Mar 11 at 17:55 Peter Cordes 368k4949 gold badges717717 silver badges981981 bronze badges asked Mar 11 at 14:45 jtxkopt - STOP GENOCIDEjtxkopt - STOP GENOCIDE 1,18122 gold badges1010 silver badges2727 bronze badges 7

• 1 That's a bizarre thing to write. Any processor that supports virtual memory supports restarting after a page fault. Generally all that is required is to return from the page fault handler after fixing the fault. – prl Commented Mar 11 at 15:37
• Idempotence means that an instruction can be repeated without any negative effect. Many instructions are not idempotent, so that means that the processor has to detect the page fault before performing any steps that can't be undone. – prl Commented Mar 11 at 15:39
• 1 @prl I think they're contrasting m68k. It can take a page-fault in the middle of an instruction with a memory-indirect pre/post-increment addressing-mode, after a side-effect on the pointer in memory but before deref of that pointer. It really does save microarchitectural state to allow resuming the instruction even after context-switch. Most other ISAs only take faults at instruction boundaries, discarding partial work. Or in the case of x86 rep movsb or vpgatherdd, updating the architectural state in a well-defined way (pointers / count for string insns, or the mask for gathers) – Peter Cordes Commented Mar 11 at 17:49
• 1 @prl: But you're right, it is bizarre because idempotence seems like the wrong word. Runnig x86 inc dword [rdi] twice is different from running it once. Atomicity wrt. interrupts is how I'd describe the thing that makes it simple on most ISAs: if an instruction faults, none of its side-effects are committed to memory or registers. – Peter Cordes Commented Mar 11 at 17:54
• 1 Sounds like an example of the old joke "There are only two hard things in Computer Science: cache invalidation and naming things". I guess I can see why someone would pick "idempotent" if they were looking for a word to describe being re-runnable after a page fault without any special handling, i.e. that faulting attempts had no effect. But it's not great because idempotence has other computer-science meanings and this is somewhat different. – Peter Cordes Commented Mar 11 at 20:12

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Sorted by: Reset to default 1

This appears to be mental masturbation intended to make the simple complex. The mathematician in me cringes at the usage of "idempotence" here. Yes, there are "idempotent" instructions

MOV #1, R0

But in nearly all cases instructions are not idempotent. So why confuse students with such needless terminology.

Things a much simpler than suggested there

A processor will only allow faults in places where it can restart. On processors with instructions that can take a "long time" (such a string/memory move), they usually keep track of progresss using registers. If a page fault occurs in such an instruction, restarting picks up whether the processor left off. The processsor does not go back and restart the entire instruction.

The MOVC5/MOVC3 instructions here do that.

https://vmssoftware/docs/VAX_MACRO_INSTRUCTION_SET_REF.pdf

So does REP MOVS

https://opensecuritytraining.info/IntroX86-64_files/IntroductionToIntelx86-64-12_RepMovs-Done.pdf

If the processor allows interrupts in the middle of an instruction withut using registers for context, it has to save additional information so that the instruction can be restarted midway through..

If restarting instruction were difficult for a page fault handler, operating systems would have been screwed over decades ago.

I also note that I have never seen a +(SP) addressing mode before. I have seen -(SP) and (SP)+ but not +(SP).