Good day to everyone. I suppose the answer to my question will be no, but maybe I misunderstood something. I need to make an 8-bit flip-flop, with a preset (constant) on the RESET signal.
It would seem that we simply take the ATF16V8, put a direct or inverse RESET on the OE input. And when the OE is active, we work as a flip-flops; when inactive, we set a constant. (OE is not required in the circuit, but in registered mode ATF16V8 has OE by default)

Even if i need external circuit which repeats RESET signal to CLK, it should work for me.

PIN 1 = CLK;
PIN [9..2] = [D7..0];
PIN [19..12] = [DQ 0..7];
PIN 11 = !OE;

[DQ7..0].d = 
     [D7..0] & OE
   # ['h'60] & !OE;

But, the compiler barking on me: [0014cb] invalid input: OE

So is there any way to use OE pin value while in registered mode for ATF16V8? Or any other options for my task? (I know i can use 19V8 or 22V10, and i will if there is no way with 16V8, but it's just a kind of interest)

P.S. Tag 'FPGA' because you can not use no tag and you can not create tag without 1500 reputation. So FPGA is as close as i can find

...
So, today i find the answer, and also there is Justin N. who answered it short but right.

Here i try to describe what i find out.

I found the GAL22V10 datasheet from Lattice Semiconductor Corp. Where was the mechanism for switching microcell modes described, so together with the actual information about 16V8, it becomes clear that the answer to my question is no.

Citation:

The modes and the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below.

In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an in dividual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop’s /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array.

NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as reg istered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins

In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Out put tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either “on” (dedicated output), “off” (dedicated input), or “product-term driven” (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array

Good day to everyone. I suppose the answer to my question will be no, but maybe I misunderstood something. I need to make an 8-bit flip-flop, with a preset (constant) on the RESET signal.
It would seem that we simply take the ATF16V8, put a direct or inverse RESET on the OE input. And when the OE is active, we work as a flip-flops; when inactive, we set a constant. (OE is not required in the circuit, but in registered mode ATF16V8 has OE by default)

Even if i need external circuit which repeats RESET signal to CLK, it should work for me.

PIN 1 = CLK;
PIN [9..2] = [D7..0];
PIN [19..12] = [DQ 0..7];
PIN 11 = !OE;

[DQ7..0].d = 
     [D7..0] & OE
   # ['h'60] & !OE;

But, the compiler barking on me: [0014cb] invalid input: OE

So is there any way to use OE pin value while in registered mode for ATF16V8? Or any other options for my task? (I know i can use 19V8 or 22V10, and i will if there is no way with 16V8, but it's just a kind of interest)

P.S. Tag 'FPGA' because you can not use no tag and you can not create tag without 1500 reputation. So FPGA is as close as i can find

...
So, today i find the answer, and also there is Justin N. who answered it short but right.

Here i try to describe what i find out.

I found the GAL22V10 datasheet from Lattice Semiconductor Corp. Where was the mechanism for switching microcell modes described, so together with the actual information about 16V8, it becomes clear that the answer to my question is no.

Citation:

The modes and the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below.

In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an in dividual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop’s /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array.

NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as reg istered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins

In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Out put tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either “on” (dedicated output), “off” (dedicated input), or “product-term driven” (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array

• fpga

Share Improve this question Follow edited Mar 25 at 19:45 EugenOS asked Mar 23 at 22:04 EugenOSEugenOS 6377 bronze badges 1

• Wow. So many questions. Starting with - is there a disti on the planet who still has a 16V8 or a 22V10? – EML Commented Mar 28 at 9:51

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2 Answers 2

Sorted by: Reset to default 2

No, not without switching the whole chip to complex mode.

Maybe its not possible to use OE in the compiler? It may already have the effect you are expecting. Checkout the ATF16V8's datasheet.