2024年5月9日发(作者：md5校验工具有什么用)

晶圆突点技术，产业准备好了吗?

摘要： Wafer bumping is a technology whose inherent benefits remain

unrealized. While the economy of scale is obvious, limitations include

insufficient infrastructure and applications that justify the cost. Yet

service providers, captive and merchant operations continue to propel

the technology with advanced equipment and streamlined processes that

promise to harvest its full potential.

Wafer bumping, where interconnections are formed on an entire wafer prior

to dicing, promises tremendous technical and economic advantages over

traditional single-die packaging. Yet the introduction of wafer bumping

as a back-end process faces significant economic hurdles. Beyond

investment in infrastructure, the operations cost must compete with

sophisticated wire bonding technologies and still produce higher process

yields. Today, the percentage of bumped wafers remains very low compared

with traditional single-die packaged chips, but interest is growing as

infrastructure builds and applications justify the initial cost premium.

Once volume becomes established, cost will shift in favor of bumping,

and the technology will accelerate at a rapid adoption a

technology perspective, inherent benefits also offer advantages that

should propel the technology. An under-bump metallization (UBM)

interface layer between wafer pads and bumps provides better bonding and

a barrier to prevent materials migration. Redistribution technology,

which involves a rerouting of the interconnections of peripheral bond

pads to a new array for the package I/Os, accommodates wider pitches that

enable both UBM and larger bumps. The bumps themselves provide electrical,

mechanical and thermal interconnection, supplying direct contact between

the package and the device. This direct interconnection reduces signal

propagation delay and relieves the constraints of power and ground

distribution. Finally, replacing wire bonds with bump interconnects

reduces package size and weight.

Bump formation technologies

Two commonly used wafer bumping methods are screen deposition and

electroplating. Each has a different approach to depositing solder on

the wafer, and both have been proven in production for some years.

Applications range from under-the-hood electronics to high-end logic and

CPUs employing these bumping methods. Pitch, necessary I/O count,

start-up cost and volume are critical criteria that dictate which method

works best.

Screen deposition is a lower-cost bumping method, generally for pitches

greater than 150 μm, practiced by a number of companies today. The

process involves squeezing solder paste through a screen stencil to

deposit bumps directly to die pads on the wafer. With modified stencils,

yields are in the 99% range on all wafer sizes using both eutectic and

lead-free materials. According to Joachim Kloeser, CTO at Ekra GmbH

(B?nnigheim, Germany), special modifications to traditional screen

printers are required. For example, high-resolution vision systems to

recognize small structures, flexibility for teaching fiducials, high

alignment accuracy, integrated cleaning, automatic wafer handling and

high process repeatability must all be incorporated into a successful

wafer bumping screen printer machine.

Electroplating technology involves starting at the UBM and performing template, plate, strip,

reflow and etch series of processes to form the bump interconnections. Electroplating offers

excellent control on deposition rates and uniformity of bumps for void-free formation; variations

in bump size can be controlled to within ±1 μm. The bath chemistry and composition must be

controlled since it affects properties such as alloy composition, surface roughness or hardness, and

crystalline structure. This bumping method can produce much finer bumps in the <100 μm range,

with tighter pitches and linewidths and corresponding greater bump densities (Fig. 1). Another

benefit of electroplating is that yields significantly outperform screen deposition bumping. While

startup costs may be higher, some packaging foundries are now offering 300 mm electroplated

wafer-level packaging at very competitive prices, which will drive the overall cost more in line

with traditional packaging operations. Since the International Technology Roadmap for

Semiconductors (ITRS) forecasts continued reduction in bump pitches, lead-free and power

redistribution, electroplating will surely capture market share associated with higher-volume

operations.