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FEATURES

Easy to Use

Low Cost Solution

Higher Performance than Two or Three Op Amp Design

Unity Gain with No External Resistor

Optional Gains with One External Resistor

(Gain Range 2 to 1000)

Wide Power Supply Range (؎2.6V to ؎15V)

Available in 8-Lead PDIP and SOIC

Low Power, 1.5 mA max Supply Current

GOOD DC PERFORMANCE

0.15% Gain Accuracy (G = 1)

125 ␮V max Input Offset Voltage

1.0 ␮V/؇C max Input Offset Drift

5 nA max Input Bias Current

66 dB min Common-Mode Rejection Ratio (G = 1)

NOISE

12 nV/√Hz @ 1kHz Input Voltage Noise

0.60 ␮V

p-p

Noise (0.1 Hz to 10 Hz, G = 10)

EXCELLENT AC CHARACTERISTICS

800 kHz Bandwidth (G = 10)

10 ␮s Settling Time to 0.1% @ G = 1–100

1.2 V/␮s Slew Rate

APPLICATIONS

Transducer Interface

Low Cost Thermocouple Amplifier

Industrial Process Controls

Difference Amplifier

Low Cost Data Acquisition

REV.C

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

Low Cost

Instrumentation Amplifier

AD622

CONNECTION DIAGRAM

R

G

18R

G

–IN

27

+V

S

+IN

3

6

OUTPUT

–V

S

4

AD622

5

REF

PRODUCT DESCRIPTION

The AD622 is a low cost, moderately accurate instrumentation

amplifier that requires only one external resistor to set any gain

between 2 and 1,000. Or for a gain of 1, no external resistor

is required. The AD622 is a complete difference or subtracter

amplifier “system” while providing superior linearity and common-

mode rejection by incorporating precision laser trimmed resistors.

The AD622 replaces low cost, discrete, two or three op amp

instrumentation amplifier designs and offers good common-

mode rejection, superior linearity, temperature stability, reliabil-

ity, and board area consumption. The low cost of the AD622

eliminates the need to design discrete instrumentation amplifi-

ers to meet stringent cost targets. While providing a lower cost

solution, it also provides performance and space improvements.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700World Wide Web Site:

Fax: 781/326-8703© Analog Devices, Inc., 1999

AD622–SPECIFICATIONS

(typical @ +25؇C, V = ؎15 V, and R = 2 k⍀ unless otherwise noted)

SL

Model

GAIN

Gain Range

Gain Error

1

G = 1

G = 10

G = 100

G = 1000

Nonlinearity,

G = 1–1000

G = 1–100

Gain vs. Temperature

VOLTAGE OFFSET

Input Offset, V

OSI

Average TC

Output Offset, V

OSO

Average TC

Offset Referred to the

Input vs.

Supply (PSR)

G = 1

G = 10

G = 100

G = 1000

INPUT CURRENT

Input Bias Current

Average TC

Input Offset Current

Average TC

INPUT

Input Impedance

Differential

Common-Mode

Input Voltage Range

2

Over Temperature

Over Temperature

Common-Mode Rejection

Ratio DC to 60 Hz with

1 kΩ Source Imbalance

G = 1

G = 10

G = 100

G = 1000

OUTPUT

Output Swing

Over Temperature

Conditions

G = 1 + (50.5 k/R

G

)

Min

1

AD622

TypMax

1000

Units

V

OUT

= ±10 V

0.05

0.2

0.2

0.2

V

OUT

= ±10 V

R

L

= 10 kΩ

R

L

= 2 kΩ

Gain = 1

Gain >1

1

(Total RTI Error = V

OSI

+ V

OSO

/G)

V

S

= ±5 V to ±15 V

V

S

= ±5 V to ±15 V

V

S

= ±5 V to ±15 V

V

S

= ±5 V to ±15 V

10

10

10

–50

60

600

125

1.0

1500

15

0.15

0.50

0.50

0.50

%

%

%

%

ppm

ppm

ppm/°C

ppm/°C

µV

µV/°C

µV

µV/°C

V

S

= ±5 V to ±15 V

80

95

110

110

100

120

140

140

2.0

3.0

0.7

2.0

5.0

2.5

dB

dB

dB

dB

nA

pA/°C

nA

pA/°C

10ʈ2

10ʈ2

V

S

= ±2.6 V to ±5 V

V

S

= ±5 V to ±18 V

–V

S

+ 1.9

–V

S

+ 2.1

–V

S

+ 1.9

–V

S

+ 2.1

+V

S

– 1.2

+V

S

– 1.3

+V

S

– 1.4

+V

S

– 1.4

GΩʈpF

GΩʈpF

V

V

V

V

V

CM

= 0 V to ±10 V

66

86

103

103

R

L

= 10 kΩ,

V

S

= ±2.6 V to ±5 V

V

S

= ±5 V to ±18 V

78

98

118

118

dB

dB

dB

dB

Over Temperature

Short Current Circuit

–V

S

+ 1.1

–V

S

+ 1.4

–V

S

+ 1.2

–V

S

+ 1.6

±18

+V

S

– 1.2

+V

S

– 1.3

+V

S

– 1.4

+V

S

– 1.5

V

V

V

V

mA

–2–

REV. C

AD622

Model

DYNAMIC RESPONSE

Small Signal –3 dB Bandwidth

G = 1

G = 10

G = 100

G = 1000

Slew Rate

Settling Time to 0.1%

G = 1–100

NOISE

Voltage Noise, 1 kHz

Input, Voltage Noise, e

ni

Output, Voltage Noise, e

no

RTI, 0.1 Hz to 10 Hz

G = 1

G = 10

G = 100–1000

Current Noise

0.1 Hz to 10 Hz

REFERENCE INPUT

R

IN

I

IN

Voltage Range

Gain to Output

POWER SUPPLY

Operating Range

3

Quiescent Current

Over Temperature

TEMPERATURE RANGE

For Specified Performance

NOTES

1

Does not include effects of external resistor R

G

.

2

One input grounded. G = 1.

3

This is defined as the same supply range that is used to specify PSR.

Specifications subject to change without notice.

ConditionsMin

AD622

TypMaxUnits

1000

800

120

12

1.2

10 V Step

10

TotalRTINoise=(e

2

ni

)+(e

no

/G)

2

kHz

kHz

kHz

kHz

V/µs

µs

12

72

4.0

0.6

0.3

100

10

20

+50

–V

S

+ 1.6

1 ± 0.0015

±2.6±18

1.3

1.5

nV/√Hz

nV/√Hz

µV p-p

µV p-p

µV p-p

fA/√Hz

pA p-p

kΩ

µA

V

f = 1 kHz

V

IN+

, V

REF

= 0+60

+V

S

– 1.6

V

S

= ±2.6 V to ±18 V0.9

1.1

–40 to +85

V

mA

mA

°C

REV. C

–3–

AD622

ABSOLUTE MAXIMUM RATINGS

1

ORDERING GUIDE

SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V

InternalPowerDissipation

2

. . . . . . . . . . . . . . . . . . . . 650 mW

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . ±V

S

DifferentialInputVoltage . . . . . . . . . . . . . . . . . . . . . . . ±25V

Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite

Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C

Operating Temperature Range

AD622A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Lead Temperature Range

(Soldering10seconds) . . . . . . . . . . . . . . . . . . . . . . . +300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

2

Specification is for device in free air:

8-Lead Plastic Package: θ

JA

= 95°C/Watt

8-Lead SOIC Package: θ

JA

= 155°C/Watt

Model

AD622AN

AD622AR

AD622AR-REEL

AD622AR-REEL7

Temperature

Range

–40°C to +85°C

–40°C to +85°C

–40°C to +85°C

–40°C to +85°C

Package

Option*

N-8

SO-8

13" Reel

7" Reel

*N = Plastic DIP, SO = Small Outline.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD622 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

Typical Characteristics

(@ +25؇C, V = ؎15 V, R = 2 k⍀, unless otherwise noted)

SL

50

50

SAMPLE SIZE = 191

40

40

P

E

R

C

E

N

T

A

G

E

O

F

U

N

I

T

S

SAMPLE SIZE = 383

P

E

R

C

E

N

T

A

G

E

O

F

U

N

I

T

S

30

30

20

20

10

10

0

–1.00–0.80

00.40

–0.400.80

OUTPUT OFFSET VOLTAGE – mV

1.00

0

6

COMMON-MODE REJECTION RATIO – dB

Figure l Distribution of Output Offset VoltageFigure l Distribution of Common-Mode Rejection

–4–

REV. C

AD622

Typical Characteristics

(@ +25؇C, V = ؎15 V, R = 2 k⍀, unless otherwise noted)

SL

2

140

120

G = 1000

G = 100

G = 10

C

M

R

–

d

B

I

N

P

U

T

O

F

F

S

E

T

V

O

L

T

A

G

E

–

␮

V

1.5

100

80

1

G = 1

60

40

20

0.5

0

0123

WARM-UP TIME – Minutes

45

0

0.11101001k

FREQUENCY – Hz

10k100k1M

Figure in Input Offset Voltage vs. Warm-Up

Time

Figure vs. Frequency, RTI, Zero to 1k

Ω

Source

Imbalance

1000

180

160

V

O

L

T

A

G

E

N

O

I

S

E

–

n

V

/

H

z

GAIN = 1

P

O

S

I

T

I

V

E

P

S

R

–

d

B

140

G = 1000

120

100

80

G = 10

60

GAIN = 1000

BW LIMIT

40

0

0.1

G = 1

100

GAIN = 10

G = 100

10

GAIN = 100, 1,000

1

1101001k

FREQUENCY – Hz

10k100k

1101001k

FREQUENCY – Hz

10k100k1M

Figure e Noise Spectral Density vs. Frequency,

(G = 1–1000)

Figure ve PSR vs. Frequency, RTI (G = 1–1000)

1000

180

160

C

U

R

R

E

N

T

N

O

I

S

E

–

f

A

/

H

z

140

N

E

G

A

T

I

V

E

P

S

R

–

d

B

120

100

80

G = 100

60

G = 10

40

G = 1

1101001k

FREQUENCY – Hz

10k100k1M

100

G = 1000

10

010

100

FREQUENCY – Hz

1000

0

0.1

Figure t Noise Spectral Density vs. Frequency

Figure ve PSR vs. Frequency, RTI (G = 1–1000)

REV. C

–5–

AD622–Typical Characteristics

(@ +25؇C, V

S

= ؎15 V, R

L

= 2 k⍀, unless otherwise noted)

1000

100

V

/

V

–

N

10

I

A

G

1

0

1001k10k100k1M10M

FREQUENCY – Hz

Figure vs. Frequency

30

V

S

= ؎15V

p

-

G = 10

p

t

s

l

o

V

–

20

N

G

I

W

S

A

G

E

T

L

V

O

10

T

U

T

P

U

O

0

101001k10k

LOAD RESISTANCE – ⍀

Figure Voltage Swing vs. Load Resistance

20

15

s

␮

–

E

M

TO 0.1%

I

T

10

N

G

I

L

T

T

E

S

5

0

05101520

OUTPUT STEP SIZE – Volts

Figure ng Time vs. Step Size (G = 1)

1000

s

␮

–

100

E

M

I

T

N

G

I

L

T

T

E

S

10

1

1101001000

GAIN

Figure ng Time to 0.1% vs. Gain, for a 10V Step

10µV

2V

100

90

ø

10

0%

Figure Nonlinearity, G = 1, R

L

= 10k

Ω

(20

µ

V = 2ppm)

10k⍀1k⍀10k⍀

0.01%10T0.1%

INPUT

20V p-p

100k⍀

0.1%

V

OUT

+V

S

11k⍀1k⍀100⍀

0.1%0.1%0.1%

G=1000

G=1

G=100

G=10

AD622

51.1⍀511⍀5.62k⍀

–V

S

Figure ng Time Test Circuit

–6–

REV. C

AD622

THEORY OF OPERATION

Make vs. Buy:A Typical Application Error Budget

The AD622 is a monolithic instrumentation amplifier based on

a modification of the classic three op-amp approach. Absolute

value trimming allows the user to program gain accurately (to

0.5% at G = 100) with only one resistor. Monolithic construc-

tion and laser wafer trimming allow the tight matching and

tracking of circuit components, thus insuring its performance.

The input transistors Q1 and Q2 provide a single differential-

pair bipolar input for high precision. Feedback through the

Q1-A1-R1 loop and the Q2-A2-R2 loop maintains constant

collector current of the input devices Q1, Q2 thereby impressing

the input voltage across the external gain-setting resistor R

G

.

This creates a differential gain from the inputs to the A1/A2

outputs given by G = (R1 + R2)/R

G

+ 1. The unity-gain sub-

tracter A3 removes any common-mode signal, yielding a

single-ended output referred to the REF pin potential.

The value of R

G

also determines the transconductance of the

preamp stage. As R

G

is reduced for larger gains, the transcon-

ductance increases asymptotically to that of the input transistors.

This has three important advantages: (a) Open-loop gain is

boosted for increasing programmed gain, thus reducing gain-

related errors. (b) The gain-bandwidth product (determined by

C1, C2 and the preamp transconductance) increases with pro-

grammed gain, thus optimizing frequency response. (c) The

input voltage noise is reduced to a value of 12 nV/√Hz, deter-

mined mainly by the collector current and base resistance of the

input devices.

The internal gain resistors, R1 and R2, are trimmed to an abso-

lute value of 25.25 kΩ, allowing the gain to be programmed

accurately with a single external resistor.

The AD622 offers a cost and performance advantages over

discrete “two op-amp” instrumentation amplifier designs along

with smaller size and less components. In a typical application

shown in Figure 14, a gain of 10 is required to receive and am-

plify a 0–20 mA signal from the AD694 current transmitter.

The current is converted to a voltage in a 50Ω shunt. In appli-

cations where transmission is over long distances, line imped-

ance can be significant so that differential voltage measurement

is essential. Where there is no connection between the ground

returns of transmitter and receiver, there must be a dc path from

each input to ground, implemented in this case using two 1kΩ

resistors. The error budget detailed in Table I shows how to

calculate the effect various error sources have on circuit accuracy.

The AD622 provides greater accuracy at lower cost. The higher

cost of the “homebrew” circuit is dominated in this case by the

matched resistor network. One could also realize a “homebrew”

design using cheaper discrete resistors which would be either

trimmed or hand selected to give high common-mode rejection.

This level of common-mode rejection would however degrade

significantly over temperature due to the drift mismatch of the

discrete resistors.

Note that for the homebrew circuit, the LT1013 specification

for noise has been multiplied by √2. This is because a “two op-

amp” type instrumentation amplifier has two op amps at its

inputs, both contributing to the overall noise.

1/2

LT1013

R

L2

10⍀

V

IN

50⍀

1k⍀

R

G

5.62k⍀

1k⍀

AD694

0–20mA

TRANSMITTER

0–20mA

R

L2

10⍀

AD622

REFERENCE

1k⍀

9k⍀*

1/2

LT1013

1k⍀

1k⍀*1k⍀*9k⍀*

*0.1% RESISTOR MATCH, 50ppm/C TRACKING

0–20mA Current Loop

with 50

Ω

Shunt Impedance

AD622 Monolithic

Instrumentation Amplifier,

G = 9.986

Figure vs. Buy

“Homebrew” In Amp, G = 10

REV. C

–7–

AD622

Table vs. Buy Error Budget

Total Error

in ppm

Relative to 1 V FS

AD622

400

2.5

25

427.5

3300

210

0.12

3510.12

10

0.6

10.6

3948

Total Error

in ppm

Relative to 1 V FS

Homebrew

1600

15

50

1665

3000

1080

9.3

4089.3

20

0.778

20.778

5575

Error Source

ABSOLUTE ACCURACY at T

A

= +25°C

Total RTI Offset Voltage, µV

Input Offset Current, nA

CMR, dB

DRIFT TO +85°C

Gain Drift, ppm/°C

Total RTI Offset Voltage, µV/°C

Input Offset Current, pA/°C

RESOLUTION

Gain Nonlinearity, ppm of Full Scale

Typ 0.1 Hz–10 Hz Voltage Noise, µV p-p

AD622 Circuit

Calculation

250 µV + 1500 µV/10

2.5 nA ×1kΩ

86 dB→50 ppm × 0.5 V

“Homebrew” Circuit

Calculation

800µV × 2

15 nA × 1 kΩ

(0.1% Match × 0.5 V)/10 V

Total Absolute Error

(50 ppm + 5 ppm) × 60°C(50 ppm)/°C × 60°C

(2µV/°C + 15 µV/°C/10) × 60°C9µV/°C × 2 × 60°C

2 pA/°C ×1kΩ × 60°C155 pA/°C ×1kΩ × 60°C

Total Drift Error

10 ppm

0.6 µV p-p

20 ppm

0.55 µV p-p × √2

Total Resolution Error

Grand Total Error

GAIN SELECTIONTable ed Values of Gain Resistors

Desired

Gain

2

5

10

20

33

40

50

65

100

200

1% Std Table

Value of R

G

, ⍀

51.1 k

12.7 k

5.62 k

2.67 k

1.58 k

1.3 k

1.02k

787

511

255

Calculated

Gain

1.988

4.976

9.986

19.91

32.96

39.85

50.50

65.17

99.83

199.0

The AD622’s gain is resistor programmed by R

G

, or more pre-

cisely, by whatever impedance appears between Pins 1 and 8.

The AD622 is designed to offer gains as close as possible to

popular integer values using standard 1% resistors. Table II

shows required values of R

G

for various gains. Note that for

G = 1, the R

G

pins are unconnected (R

G

=∞). For any arbitrary

gain R

G

can be calculated by using the formula

50.5kΩ

R

G

=

G−1

To minimize gain error avoid high parasitic resistance in series

with R

G

, and to minimize gain drift, R

G

should have a low

TC—less than 10 ppm/°C for the best performance.

500

1000

102

51.1

496.1

989.3

–8–

REV. C

AD622

INPUT AND OUTPUT OFFSET VOLTAGE

RF INTERFERENCE

The low errors of the AD622 are attributed to two sources,

input and output errors. The output error is divided by G when

referred to the input. In practice, the input errors dominate at

high gains and the output errors dominate at low gains. The

total V

OS

for a given gain is calculated as:

Total Error RTI = input error + (output error/G)

Total Error RTO = (input error × G) + output error

REFERENCE TERMINAL

The circuit of Figure 15 is recommended for AD622 series in-

amps and provides good RFI suppression at the expense of

reducing the (differential) bandwidth. In addition, this RC input

network also provides additional input overload protection (see

input protection section). Resistors R1 and R2 were selected to

be high enough in value to isolate the circuit’s input from ca-

pacitors C1–C3, but without significantly increasing the circuit’s

noise.

C1

1000pF 5%

R1

4.02k⍀ 1%

–IN

C3

0.047␮F

+IN

3

1

R

G

8

7

+V

S

0.33␮F

0.01␮F

The reference terminal potential defines the zero output voltage

and is especially useful when the load does not share a precise

ground with the rest of the system. It provides a direct means of

injecting a precise offset to the output, with an allowable range

of 2 V within the supply voltages. Parasitic resistance should be

kept to a minimum for optimum CMR.

INPUT PROTECTION

AD622

5

4

2

6

V

OUT

The AD622 features 400 Ω of series thin film resistance at its

inputs, and will safely withstand input overloads of up to ±25 V

or ±60 mA for up to an hour. This is true for all gains and

power on and off, which is particularly important since the

signal source and amplifier may be powered separately. For

continuous input overload, the current should not exceed 6 mA

(I

IN

≤ V

IN

/400 Ω). For input overloads beyond the supplies,

clamping the inputs to the supplies (using a diode such as an

IN4148) will reduce the required resistance, yielding lower

noise.

R2

4.02k⍀ 1%

C2

1000pF 5%

0.33␮F

0.01␮F

LOCATE C1–C3 AS CLOSE TO

THE INPUT PINS AS POSSIBLE

–V

S

Figure Suppression Circuit for AD622 Series In-Amps

R1/R2 and C1/C2 form a bridge circuit whose output appears

across the in-amp’s input pins. Any mismatch between the C1/

R1 and C2/R2 time constant will unbalance the bridge and

reduce common-mode rejection. C3 insures that any RF signals

are common mode (the same on both in-amp inputs) and are

not applied differentially.

This low pass network has a –3dB BW equal to: 1/(2π (R1 +

R2) (C3 + C1 + C2)). Using a C3 value of 0.047µF as shown,

the –3dB signal BW of this circuit is approximately 400Hz.

When operating at a gain of 1000, the typical dc offset shift over

a frequency range of 1Hz to 20MHz will be less than 1.5µV

RTI and the circuit’s RF signal rejection will be better than

71dB. At a gain of 100, the dc offset shift is well below 1mV

RTI and RF rejection better than 70dB.

The 3dB signal bandwidth of this circuit may be increased to

900Hz by reducing resistors R1 and R2 to 2.2kΩ. The perfor-

mance is similar to that using 4kΩ resistors, except that the

circuitry preceding the in-amp must drive a lower impedance

load.

This circuit should be built using a PC board with a ground

plane on both sides. All component leads should be made as

short as possible. Resistors R1 and R2 can be common 1%

metal film units but capacitors C1 and C2 need to be ±5%

tolerance devices to avoid degrading the circuit’s common-mode

rejection. Either the traditional 5% silver micas, miniature size

micas, or the new Panasonic ±2% PPS film capacitors are

recommended.

REV. C

–9–

AD622

GROUNDINGGROUND RETURNS FOR INPUT BIAS CURRENTS

Since the AD622 output voltage is developed with respect to the

potential on the reference terminal, it can solve many grounding

problems by simply tying the REF pin to the appropriate “local

ground.” The REF pin should however be tied to a low imped-

ance point for optimal CMR.

The use of ground planes is recommended to minimize the

impedance of ground returns (and hence the size of dc errors).

In order to isolate low level analog signals from a noisy digital

environment, many data-acquisition components have separate

analog and digital ground returns (Figure 16). All ground pins

from mixed signal components such as analog to digital converters

should be returned through the “high quality” analog ground

plane. Maximum isolation between analog and digital is

achieved by connecting the ground planes back at the supplies.

The digital return currents from the ADC which flow in the

analog ground plane will in general have a negligible effect on

noise performance.

ANALOG P.S.

+5V–5V

C

Input bias currents are those currents necessary to bias the input

transistors of an amplifier. There must be a direct return path

for these currents; therefore when amplifying “floating” input

sources such as transformers, or ac-coupled sources, there must

be a dc path from each input to ground as shown in Figure 17.

Refer to the Instrumentation Amplifier Application Guide (free

from Analog Devices) for more information regarding in amp

applications.

+V

S

–INPUT

2

1

7

R

G

8

3

AD622

5

4

6

V

OUT

LOAD

+INPUT

–V

S

REFERENCE

TO POWER

SUPPLY

GROUND

DIGITAL P.S.

C+5V

Figure Returns for Bias Currents with

Transformer Coupled Inputs

+V

S

–INPUT

2

1

7

0.1␮F

0.1␮F

0.1␮F

R

G

8

AD622

5

4

3

6

V

OUT

LOAD

V

DD

AGNDDGND

12

V

DD

GND

AD622

V

IN

1

V

IN

2

AD7892-2

␮PROCESSOR

+INPUT

REFERENCE

–V

S

TO POWER

SUPPLY

GROUND

Figure Grounding Practice

Figure Returns for Bias Currents with

Thermocouple Inputs

+V

S

–INPUT

R

G

AD622

LOAD

V

OUT

+INPUT

100k⍀100k⍀

–V

S

REFERENCE

TO POWER

SUPPLY

GROUND

Figure Returns for Bias Currents with

AC Coupled Inputs

–10–

REV. C

AD622

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Plastic DIP (N-8) Package

REV. C

0.430 (10.92)

0.348 (8.84)

8

5

0.280 (7.11)

0.240 (6.10)

14

0.325 (8.25)

PIN 1

0.060 (1.52)

0.300 (7.62)

0.210 (5.33)

0.015 (0.38)

0.195 (4.95)

MAX

0.130

0.115 (2.93)

0.160 (4.06)

(3.30)

0.115 (2.93)

MIN

SEATING

0.015 (0.381)

0.022 (0.558)

0.100

0.070 (1.77)

PLANE

0.008 (0.204)

0.014 (0.356)

(2.54)

BSC

0.045 (1.15)

SOIC (SO-8) Package

0.1968 (5.00)

0.1890 (4.80)

0.1574 (4.00)

8

5

0.2440 (6.20)

0.1497 (3.80)

14

0.2284 (5.80)

PIN 1

0.0688 (1.75)

0.0196 (0.50)

0.0098 (0.25)0.0532 (1.35)

0.0099 (0.25)

x 45°

0.0040 (0.10)

8°

SEATING

0.0500

0.0192 (0.49)

PLANE

(1.27)

0.0098 (0.25)

0°

0.0500 (1.27)

BSC

0.0138 (0.35)

0.0075 (0.19)0.0160 (0.41)

–11–

9

9

/

4

–

0

–

c

8

1

1

2

C

P

R

I

N

T

E

D

I

N

U

.

S

.

A

.