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A10GbsBiCMOSAdaptiveCableEqualizer_slicer_DETAIL

A 10Gb/s BiCMOS Adaptive Cable Equalizer

Guangyu Evelina Zhang ,Student Member,IEEE,and Michael ,Member,IEEE

Abstract—A 10Gb/s adaptive equalizer IC using SiGe BiCMOS technology is circuit consists of the

combination of an analog equalizer and an adaptive feedback loop for minimizing the inter-symbol interference (ISI)for a

variety of cable adaptive loop functions using a novel slope-detection circuit which has a characteristic

that correlates closely with the amount of chip occupies an area of 0.87

mm 0.81mm and consumes a power of 350mW with 3.3V power adaptive equalizer is able to compensate for a

cable loss up to 22dB at 5GHz while maintaining a low bit-error rate.

Index Terms—Adaptive equalizers,broadband communication,BiCMOS,BiCMOS analog integrated circuits,equalizers,wire

communication cable.

I.I NTRODUCTION

A

S BIT RATES increase in broadband data communica-tion systems,the nonideal effects of the channel have an increasingly

important impact on the quality of the particular,the loss (caused by skin effect and dielectric loss)in copper causes

signi?cant attenuation of the transmitted data at high bit rates of 10Gb/s and higher,even a rela-tively short

section of copper can cause signi?cant distortion of the order to avoid bit errors and successfully receive the data

signal,equalization is often the exact char-acteristic of the channel is not known,adaptive equalization is

desirable.

A block diagram of a typical receiver is shown in equalizer is the ?rst block in the receiver,after which the re-stored

data is then applied to the an example of a copper cable characteristic,Fig.2shows the measured trans-mission

characteristic for two RU-256copper cables,one with length 4feet;the other with length 5GHz the 4-foot cable

exhibits a loss of 5d

B at 5GHz;the 15-foot cable ex-hibits a loss of 13dB,which would result in a completely closed of the goals of this

circuit design was to make the circuit adaptive such that the inter-symbol interference (ISI)is minimized for a wide range of

cable theory,the transfer function of a copper cable should be monotonically

nonmonotonicities in Fig.2are due to re?ec-tions that come from discontinuities in the connectors and mis-matches between

the cables and the measurement general the analog equalizer presented in this paper is not well-suited for

media that exhibit large amounts of re?r,as will be demonstrated shortly,for the characteristics

Manuscript received January 14,2005;revised July 18, work was supported by Qlogic,Jazz Semiconductor,and UC

Discovery Grant Com 01-10086.

The authors are with the Department of Electrical Engineering and Com-puter Science,University of California,Irvine,CA

92697-2625USA (e-mail:mgreen@/doc/ ).

Digital Object Identi?er 10.1109/JSSC.2005.857354

shown in Fig.2the equalizer described here has been shown to function well.

At relatively low bit rates,most adaptive equalizers have been implemented using a digital approach [1],[2].Design of a dig-

ital equalizer at the receiver side involves a delay element and a decision circuit that requires a recovered

extraction of the clock depends on the input data of the clock and data re-covery (CDR)circuit,which increases the system

complexity and could lead to problems with CDR the other hand,an analog approach is often preferred for higher

speeds for its low power consumption and simplicity.A number of papers have been reported on analog cable equalization at

bit rates on the order of 100Mb/s [3]–[5].Recently,two papers re-ported cable equalizers with bit-rates up to 3.5Gb/s [6],[7].In

this paper,we present an analog adaptive equalizer running at 10Gb/s using a BiCMOS fabrication recently,a

CMOS equalizer operating at 10Gb/s was presented [8]where more design effort was needed to overcome the gain

limitations of analog FIR approach to 10Gb/s equalization was presented in [9].

A BiCMOS process was chosen for this design due to both

the

high

and high intrinsic gain of the bipolar particular,it was critical that the slicer used in the adaptive feedback loop

(explained in Section III)exhibited high gain in order to restore the logic levels.

This paper,which is an expanded version of the paper pre-sented in [10],is organized as n II discusses the

principle of operation for the equalizer and adaptive n III describes the circuit design details for each

ement results of prototypes are presented in Section IV .Finally,conclusions are drawn in Section V .

II.P RINCIPLE OF O PERATION

To understand the equalizer’s operation,we ?rst consider the operation of a simpli?ed linear circuit,shown in Fig.3oper-ating

at a bit rate normalized to 1b/s.A rudimentary cable model shown in Fig.3(a),consisting of four RC sections,is used for this

mentioned in the previous section,this medium exhibits a monotonically decreasing transfer ,we

would expect the ISI to be dominated by the attenu-ation of short (i.e.,1UI) other words,the worst ISI would come

from an isolated logic “1”of duration 1UI sur-rounded by strings of logic “0.”This is illustrated in Fig.4,

where the response of the Fig.3(a)cable model,

with

set to 0.188,is shown for three different input pulse widths:1s,2s,and y the worst case ISI comes from the shortest

pulse ,our approach for designing the equalizer and adaptation loop is to reduce the ISI of a single

pulse,described as follows.

0018-9200/$20.00?2005IEEE

diagram of broadband receiver including equalizer.

TABLE I

O PTIMUM T RANSIENT C HARACTERISTICS OF E QUALIZER FOR T HREE D IFFERENT C ABLE M

ODELS