2024年4月16日发(作者：华为5g手机最新消息)

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HCPL-0872

Digital Interface IC

Data Sheet

Lead (Pb) Free

RoHS 6 fully

compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

Description

The Digital Interface IC, HCPL-0872 converts the single-

bit data stream from the Isolated Modulator (such as

HCPL-7860/786J/7560) into fifteen-bit output words and

provides a serial output interface that is compatible with

SPI

®

, QSPI

®

, and Microwire

®

protocols, allowing direct

connection to a microcontroller. The Digital Interface IC,

HCPL-0872 is available in a 300-mil wide SO-16 surface-

mount package. Features of the Digital Interface IC

include five different conversion modes, three different

pre-trigger modes, offset calibration, fast over-range

detection, and adjustable threshold detection. Program-

mable features are configured via the Serial Configura-

tion port. A second multiplexed input is available to allow

measurements with a second isolated modulator without

additional hardware.

Features

• Interface between HCPL-7860/786J/7560 and MCU/

DSP

• 5 Conversion Modes for Resolution/Speed Trade-Off

• 3 Pre-Trigger Modes

• Offset Calibration

• Fast 3 µs Over-Range Detection

• Adjustable Threshold Detection

• Serial I/O (SPI

®

, QSPI

®

and Microwire Compatible)

• Offset Calibration

• -40°C to +85°C Operating Temperature Range

Applications

• Motor Phase and Rail Current Sensing

• Data Acquisition Systems

• Industrial Process Control

• Inverter Current Sensing

• General Purpose Current Sensing and Monitoring

V

DD1

Input

Current

V

DD2

MCLK

MDAT

GND2

1

2

3

4

5

6

7

8

CCLK

V

IN+

V

IN--

GND1

CONFIG

-

CLAT

INTER-

CHAN

FACE

CON

VERSION

CDATSCLK

INTER--

FACE

V

DD

16

15

14

13

12

11

10

9

MCLK1

MDAT1

MCLK2

SDAT

HCPL-7860

HCPL-786J

HCPL-7560

V

DD1

Input

Current

CH1

CS

THR1

MCU

or

DSP

V

DD2

MCLK

MDAT

GND2

V

IN+

V

IN--

GND1

THRES

MDAT2

CH2

HOLD

OVR1

DETECT

& RESET

GNDRESET

HCPL-0872

A 0.1 µF bypass capacitor must be connected between pins V

DD

and Ground

CAUTION: It is advised that normal static precautions be taken in handling and assembly

of this component to prevent damage and/or degradation, which may be induced by ESD.

SPI and QSPI are trademarks of Motorola Corp.

Microwire is a trademark of National Semiconductor Inc.

元器件交易网

HCPL-0872 Digital Interface IC

Because the two inputs are multiplexed, only one con-

version at a time can be made and not all features are

available for the second channel. The available features

for both channels are shown in the table below

Feature

Conversion Mode

Offset Calibration

Pre-Trigger Mode

Over-Range Detection

Adjustable Threshold

Detection

Channel 1

•

•

•

•

•

Channel 2

•

•

CCLK

1

CLAT

2

CDAT

3

MCLK1

4

MDAT1

5

MCLK2

6

MDAT2

7

GND

8

CH2

CONFIG.

INTER-

FACE

CON-

VERSION

INTER-

FACE

16

V

DD

15

CHAN

14

SCLK

13

SDAT

12

CS

THRES-

HOLD

DETECT

&

RESET

11

THR1

10

OVR1

9

RESET

CH1

Pin Description, Digital Interface IC

Symbol

CCLK

CLAT

CDAT

MCLK1

MDAT1

MCLK2

MDAT2

GND

VDD

CHAN

SCLK

SDAT

Description

Clock input for the Serial Configuration Interface (SCI). Serial Configuration data is clocked in on the

rising edge of CCLK.

Latch input for the Serial Configuration Interface (SCI). The last 8 data bits clocked in on CDAT by

CCLK are latched into the appropriate configuration register on the rising edge of CLAT.

Data input for the Serial Configuration Interface (SCI). Serial configuration data is clocked in MSB

first.

Channel 1 Isolated Modulator clock input. Input Data on MDAT1 is clocked in on the rising edge of

MCLK1.

Channel 1 Isolated Modulator data input.

Channel 2 Isolated Modulator clock input. Input Data on MDAT2 is clocked in on the rising edge of

MCLK2.

Channel 2 Isolated Modulator data input.

Digital ground.

Supply voltage (4.5 V to 5.5 V).

Channel select input. The input level on CHAN determines which channel of data is used during the

next conversion cycle. An input low selects channel 1, a high selects channel 2.

Serial clock input. Serial data is clocked out of SDAT on the falling edge of SCLK.

Serial data output. SDAT changes from high impedance to a logic low output at the start of a conver-

sion cycle. SDAT then goes high to indicate that data is ready to be clocked out. SDAT returns to a

high-impedance state after all data has been clocked out and CS has been brought high. SDAT goes

high immediately after RESET is released.

Conversion start input. Conversion begins on the falling edge of CS. CS should remain low during

the entire conversion cycle and then be brought high to conclude the cycle.

Continuous, programmable-threshold detection for channel 1 input data. A high level output on

THR1 indicates that the magnitude of the channel 1 input signal is beyond a user programmable

threshold level between 160 mV and 310 mV. This signal continuously monitors channel 1 indepen-

dent of the channel select (CHAN) signal.

High speed continuous over-range detection for channel 1 input data. A high level output on OVR1

indicates that the magnitude of the channel 1 input is beyond full-scale. This signal continuously

monitors channel 1 independent of the CHAN signal.

Master reset input. A logic high input for at least 100 ns asynchronously resets all configuration reg-

isters to their default values and zeroes the Offset Calibration registers.

CS

THR1

OVR1

RESET

2