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SODIMMDDR2 SDRAMDDR2 Unbuffered SODIMM200pin Unbuffered SODIMM based on 1Gb Q-die64-bit Non-ECC60FBGA & 84FBGA with Lead-Free and Halogen-Free(RoHS compliant)INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE

CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT

GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1 of 19Rev. 1.1 July 2008

SODIMMTable of ContentsDDR2 SDRAM1.0 DDR2 Unbuffered SODIMM Ordering Information .....................................................................42.0 Features .........................................................................................................................................43.0 Address Configuration .................................................................................................................44.0 Pin Configurations (Front side/Back side) .................................................................................55.0 56.0 Input/Output Function Description .............................................................................................67.0 Functional Block Diagram :......................................................................................................... 7 7.1 2GB, 256Mx64 Module - M470T5663QZ(H)3 .......................................................................................7 7.2 1GB, 128Mx64 Module - M470T2864QZ(H)3 .......................................................................................8 7.3 512MB, 64Mx64 Module - M470T6464QZ(H)3 ......................................................................................98.0 Absolute Maximum DC Ratings ................................................................................................109.0 AC & DC Operating Conditions .................................................................................................10 9.1 Recommended DC Operating Conditions (SSTL - 1.8) ......................................................................10 9.2 Operating Temperature Condition

..................................................................................................11 9.3 Input DC Logic Level ....................................................................................................................11 9.4 Input AC Logic Level ....................................................................................................................11 9.5 AC Input Test Conditions ..............................................................................................................1110.0 IDD Specification Parameters Definition ................................................................................1211.0 Operating Current Table : ........................................................................................................13 11.1 M470T5663QZ(H)3 : 256Mx64 .13 11.2 M470T2864QZ(H)3 : 128Mx64 .13 11.3 M470T6464QZ(H)3 : 64Mx64 512MB Module

....................................................................................1312.0 Input/Output Capacitance ........................................................................................................1413.0 Electrical Characteristics & AC Timing for DDR2-800/667 ...................................................14 13.1 Refresh Parameters by 14 13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ...............................................14 13.3 Timing Parameters by Speed Grade ..............................................................................................1514.0 Physical Dimensions : .............................................................................................................17 14.1 128Mbx8 based 256Mx64 Module (2 Rank) .....................................................................................17 14.2 64Mbx16 based 128Mx64 Module (2 Rank)

......................................................................................18 14.3 64Mbx16 based 64Mx64 Module (1 Rank) .......................................................................................19 2 of 19Rev. 1.1 July 2008

SODIMMRevision HistoryRevision1.01.011.1MonthSeptemberAprilJulyYear2 - Initial Release - Typo Correction - Applied JEDEC update(JESD79-2E) on AC timing tableHistoryDDR2 SDRAM 3 of 19Rev. 1.1 July 2008

SODIMM1.0 DDR2 Unbuffered SODIMM Ordering InformationPart NumberM470T5663QZ(H)3-C(L)E7/F7/E6M470T2864QZ(H)3-C(L)E7/F7/E6M470T6464QZ(H)3-C(L)E7/F7/E6Density2GB1GB512MBOrganization256Mx64128Mx6464Mx64Component Composition128Mx8(K4T1G084QQ-HC(L)E7/F7/E6)*1664Mx16(K4T1G164QQ-HC(L)E7/F7/E6)*864Mx16(K4T1G164QQ-HC(L)E7/F7/E6)*4DDR2 SDRAMNumber of RankHeight22130mm30mm30mmNote :1. “Z” of Part number(12th digit) stands for Lead-Free products.2. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.3. “3” of Part number(13th digit) stands for Dummy Pad PCB products.2.0 Features•Performance rangeE7 (DDR2-800)Speed@CL3Speed@CL4Speed@CL5Speed@CL6CL-tRCD-tRP400533800-5-5-5F7 (DDR2-800)-5336678006-6-6E6 (DDR2-667)400533667-5-5-5UnitMbpsMbpsMbpsMbpsCK•JEDEC standard VDD = 1.8V ± 0.1V Power Supply•VDDQ = 1.8V ± 0.1V•333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin•8 Banks•Posted CAS•Programmable CAS Latency: 3, 4, 5, 6•Programmable Additive Latency: 0, 1 , 2 , 3, 4, 5•Write Latency(WL) = Read Latency(RL) -1•Burst Length: 4 , 8(Interleave/Nibble sequential)•Programmable Sequential / Interleave Burst Mode•Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)•Off-Chip Driver(OCD) Impedance Adjustment

•On Die Termination with selectable values(50/75/150 ohms or disable)•Average Refresh Period 7.8us at lower than a TCASE

85°C, 3.9us at 85°C < TCASE

< 95 °C-

Support

High Temperature Self-Refresh rate enable feature•Package: 60ball FBGA - 128Mx8 and 84ball FBGA - 64Mx16•All of base components are Lead-Free, Halogen-Free, and RoHS compliant Note : For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.3.0 Address ConfigurationOrganization128Mx8(1Gb) based Module64Mx16(1Gb) based ModuleRow AddressA0-A13A0-A12Column AddressA0-A9A0-A9Bank AddressBA0-BA2BA0-BA2Auto PrechargeA10A10 4 of 19Rev. 1.1 July 2008

SODIMM4.0 Pin Configurations (Front side/Back side)Pin729343454749FrontVREFVSSDQ0DQ1VSSDQS0DQS0VSSDQ2DQ3VSSDQ8DQ9VSSDQS1DQS1VSSDQ10DQ11VSSVSSDQ16DQ17VSSDQS2Pin24684464850BackVSSDQ4DQ5VSSDM0VSSDQ6DQ7VSSDQ12DQ13VSSDM1VSSCK0CK0VSSDQ14DQ15VSSVSSDQ20DQ21VSSNCPin5636567697838587899193959799FrontDQS2VSSDQ18DQ19VSSDQ24DQ25VSSDM3NCVSSDQ26DQ27VSSCKE0VDDNCBA2VDDA12A9A8VDDA5A3Pin525456586274767882949698100BackDM2VSSDQ22DQ23VSSDQ28DQ29VSSDQS3DQS3VSSDQ30DQ31VSSNC/CKE1VDDNCNCVDDA11A7A6VDDA4A2Pin3397149FrontA1VDDA10/APBA0WEVDDCASNC/S1VDDNC/ODT1VSSDQ32DQ33VSSDQS4DQS4VSSDQ34DQ35VSSDQ40DQ41VSSDM5VSSPin8150BackA0VDDBA1RASS0VDDODT0A13VDDNCVSSDQ36DQ37VSSDM4VSSDQ38DQ39VSSDQ44DQ45VSSDQS5DQS5VSSPin753897199DDR2 SDRAMFrontDQ42DQ43VSSDQ48DQ49VSSNC, TESTVSSDQS6DQS6VSSDQ50DQ51VSSDQ56DQ57VSSDM7VSSDQ58DQ59VSSSDASCLVDDSPDPin88200BackDQ46DQ47VSSDQ52DQ53VSSCK1CK1VSSDM6VSSDQ54DQ55VSSDQ60DQ61VSSDQS7DQS7VSSDQ62DQ63VSSSA0SA1Note : NC = No Connect; NC, TEST(pin 163)is for bus analysis tool and is not connected on normal memory modules.5.0 Pin DescriptionPin NameCK0,CK1CK0,CK1CKE0,CKE1RASCASWES0,S1A0~A9, A11~A13A10/APBA0~BA2ODT0,ODT1SCLCK0,CK1DescriptionClock Inputs, positive lineClock Inputs, negative lineClock EnablesRow Address StrobeColumn Address StrobeWrite EnableChip SelectsAddress InputsAddress Input/AutoprechargeSDRAM Bank AddressOn-die termination controlSerial Presence Detect(SPD) Clock InputClock Inputs, positive linePin NameSDASA1,SA0DQ0~DQ63DM0~DM7DQS0~DQS7DQS0~DQS7TESTVDDVSSVREFVDDSPDNCSDASPD addressData Input/OutputData MasksData strobesData strobes complementLogic Analyzer specific test pin

(No connect on So-DIMM)Core and I/O PowerGroundInput/Output ReferenceSPD PowerSpare pins, No connectSPD Data Input/OutputDescriptionSPD Data Input/Output*The VDD and VDDQ pins are tied to the single power-plane on PCB. 5 of 19Rev. 1.1 July 2008

SODIMM6.0 Input/Output Function DescriptionSymbolCK0-CK1CK0-CK1CKE0-CKE1TypeInputDescriptionDDR2 SDRAMThe system clock inputs. All address and command lines are sampled on the cross point of the rising edge

of CK and falling edge of CK . A Delay Locked Loop (DLL) circuit is driven from the clock input and output

timing for read operations is synchronized to the input tes the DDR2 SDRAM CK signal when high and deactivates the CK signal when low, By deactivating

the clocks, CKE low initiates the Power Down mode or the Self Refesh s the associated DDR2 SDRAM command decoder when low and disables the command decoder

when high. When the command decoder is disabled, new commands are ignored but previous operations

continue. Rank 0 is selected by S0, Rank 1 is selected by S1. Ranks are also called “Physical banks”.When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS, and WE

define the operation to be executed by the s which DDR2 SDRAM internal bank is s on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM ExtendedMode Register Set (EMRS).During a Bank Activate command cycle, defines the row address when sampled at the cross point of therising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the columnaddress when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to thecolumn address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. IfAP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, auto-precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to con-trol which bank(s) to precharge. If AP is high, all banks will be pecharged regardiess of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to Input/Output data write masks, associated with one data byte. In Write mode, DM operates as a byte

mask by allowing input data to be written if it is low but blocks the write operation if it is high. In

Read mode, DM lines have no data strobes, associated with one data byte, sourced with data transfers. In Write mode, the datastrobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe issourced by the DDR2 SDRAMs and is sent at the leading edge of the data window. DQS signals are com-plements, and timing is relative to the crosspoint of respective DQS and DQS If the module is to be oper-ated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2SDRAM mode registers programmed supplies for core, I/O, Serial Presence Detect, and ground for the is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be con-nected to VDD to act as a pull signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCLto VDD to act as a pull s pins used to select the Serial Presence Detect base TEST pin is reserved for bus analysis tools and is not connected on normal memory modules(SO-DIMMs).InputS0-S1Input RAS, CAS, WEBA0~BA2ODT0~ODT1InputInputInputA0~A9,A10/AP,A11~A13InputDQ0~DQ63DM0~DM7In/OutInputDQS0~DQS7DQS0~DQS7In/OutVDD,VDDSPD,VSSSDASCLSA0~SA1TESTSupplyIn/OutInputInputIn/Out 6 of 19Rev. 1.1 July 2008

SODIMM7.0 Functional Block Diagram :7.1 2GB, 256Mx64 Module - M470T5663QZ(H)3(Populated as 2 ranks of x8 DDR2 SDRAMs)3Ω + 5%

CKE1ODT1S1CKE0ODT0S0DQS0DQS0DM0DQSDQSDMI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7CS0ODT0CKE0DDR2 SDRAMDQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7D0DQSDQSDMI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7CS1ODT1CKE1DQS4DQS4DM4D8DQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39DQSDQSDMI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7CS0ODT0CKE0D4DQSDQSDMI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7CS1ODT1CKE1D12DQS1DQS1DM1DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15CS0ODQSDQSDDMT0I/O 8I/O 9D1I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15CKE0CS1ODQSDQSDDMT1I/O 8I/O 9D9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15CKE1DQS5DQS5DM5DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47DQSDQSDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15CS0ODT0CKE0D5DQSDQSDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15CS1ODT1CKE1D13DQS2DQS2DM2DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQSDQSDMI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7CS0ODT0CKE0D2DQSDQSDMI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7CS1ODT1CKE1DQS6DQS6DM6D10DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55DQSDQSDMI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7CS0ODT0CKE0D6DQSDQSDMI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7CS1ODT1CKE1D14DQS3DQS3DM3DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31CS0ODQSDDQSTDM0I/O 8I/O 9D3I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15CKE0CS1ODQSDDQSTDM1I/O 8I/O 9D11I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15CKE1DQS7DQS7DM7DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63DQSDQSDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15CS0ODT0CKE0D7DQSDQSDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15CS1ODT1CKE1D1510Ω + 5%

BA0 - BA2A0 - A13RASCASWEDDR2 SDRAMs D0 - D15DDR2 SDRAMs D0 - D15DDR2 SDRAMs D0 - D15DDR2 SDRAMs D0 - D15DDR2 SDRAMs D0 - D15SCLSA0SA1SCLA0SPDA1A2WPSDA* Clock WiringClock Input*CK0/CK0*CK1/CK1 DDR2 SDRAMs8 DDR2 SDRAMs8 DDR2 SDRAMsVDDSPDVREFVDDVSSSerial PDDDR2 SDRAMs D0 - D15DDR2 SDRAMs D0 - D15, VDD

and VDDQDDR2 SDRAMs D0 - D15, SPD* Wire per Clock Loading

Table/Wiring DiagramsNote :

1. DQ,DM, DQS/DQS resistors : 22 Ohms

± 5%.

2. BAx, Ax, RAS, CAS, WE resistors : 10.0 Ohms

± 5%.

7 of 19Rev. 1.1 July 2008

SODIMMDDR2 SDRAM7.2 1GB, 128Mx64 Module - M470T2864QZ(H)3(Populated as 2 rank of x16 DDR2 SDRAMs)3Ω + 5%

ODT1ODT0CKE1CKE0S1S0DQS0DQS0DM0LDQSCSCKLDQSELDMI/O 0I/O 1D0I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7UDQSUDQSUDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15LDQSCSCKLDQSELDMI/O 0I/O 1D1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7UDQSUDQSUDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15ODTDQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQS1DQS1DM1DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15LDQSCSCKLDQSELDMI/O 0I/O 1D4I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7UDQSUDQSUDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15LDQSCSCKLDQSELDMI/O 0I/O 1D5I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7UDQSUDQSUDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15ODTDQS4DQS4DM4DQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39DQS5DQS5DM5DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47LDQSCSCKLDQSELDMI/O 0I/O 1D2I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7UDQSUDQSUDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15LDQSCSCKLDQSELDMI/O 0I/O 1D3I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7UDQSUDQSUDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15ODTLDQSCSCKLDQSELDMI/O 0I/O 1D6I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7UDQSUDQSUDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15LDQSCSCKLDQSELDMI/O 0I/O 1D7I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7UDQSUDQSUDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15ODTDQS2DQS2DM2ODTODTDQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQS6DQS6DM6ODTODTDQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55DQS3DQS3DM3DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31DQS7DQS7DM7DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ633Ω + 5%

BA0 - BA2A0 - A13RASCASWEDDR2 SDRAMs D0 - D7DDR2 SDRAMs D0 - D7DDR2 SDRAMs D0 - D7DDR2 SDRAMs D0 - D7DDR2 SDRAMs D0 - D7SCLSA0SA1SCLA0A1A2SPDSDAWP* Clock WiringVDDSPDVREFVDDVSSSerial PDDDR2 SDRAMs D0 - D7DDR2 SDRAMs D0 - D7, VDD

and VDDQDDR2 SDRAMs D0 - D7, SPDClock Input*CK0/CK0*CK1/CK1 DDR2 SDRAMs4 DDR2 SDRAMs4 DDR2 SDRAMs* Wire per Clock Loading

Table/Wiring DiagramsNote :

1. DQ,DM, DQS/DQS resistors : 22 Ohms

± 5%.

2. BAx, Ax, RAS, CAS, WE resistors : 3.0 Ohms

± 5%.

8 of 19Rev. 1.1 July 2008

SODIMMDDR2 SDRAM7.3 512MB, 64Mx64 Module - M470T6464QZ(H)3

(Populated as 1 rank of x16 DDR2 SDRAMs)3Ω + 5%

CKE0ODT0S0DQS0DQS0DM0LDQSCSODLDQSTLDMI/O 0I/O 1D0I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7UDQSUDQSUDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15LDQSCSODLDQSTLDMI/O 0I/O 1D1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7UDQSUDQSUDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15CKEDQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQS4DQS4DM4DQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39DQS1DQS1DM1DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15DQS5DQS5DM5DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47LDQSCSODLDQSTLDMI/O 0I/O 1D2I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7UDQSUDQSUDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15LDQSCSODLDQSTLDMI/O 0I/O 1D3I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7UDQSUDQSUDMI/O 8I/O 9I/O 10I/O 11I/O 12I/O 13I/O 14I/O 15CKEDQS2DQS2DM2CKEDQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQS6DQS6DM6CKEDQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55DQS3DQS3DM3DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31DQS7DQS7DM7DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ633Ω + 5%

BA0 - BA2A0 - A13RASCASWEDDR2 SDRAMs D0 - D3DDR2 SDRAMs D0 - D3DDR2 SDRAMs D0 - D3DDR2 SDRAMs D0 - D3DDR2 SDRAMs D0 - D3SCLSA0SA1SCLA0SPDA1A2WPSDA* Clock WiringClock Input*CK0/CK0*CK1/CK1VDDSPDVREFVDDVSSSerial PDDDR2 SDRAMs D0 - D3DDR2 SDRAMs D0 - D3, VDD

and VDDQDDR2 SDRAMs D0 - D3, SPD DDR2 SDRAMs2 DDR2 SDRAMs2 DDR2 SDRAMs* Wire per Clock Loading

Table/Wiring DiagramsNote :

1. DQ,DM, DQS/DQS resistors : 22 Ohms

± 5%.

2. BAx, Ax, RAS, CAS, WE resistors : 3.0 Ohms ± 5%.

9 of 19Rev. 1.1 July 2008

SODIMM8.0 Absolute Maximum DC Ratings

Symbol VDDVDDQ

VDDLVIN,

VOUT

TSTG

Parameter

Voltage on VDD pin relative to VSSVoltage on VDDQ pin relative to VSSVoltage on VDDL pin relative to VSSVoltage on any pin relative to VSSStorage Temperature

Rating- 1.0 V ~ 2.3 V- 0.5 V ~ 2.3 V- 0.5 V ~ 2.3 V- 0.5 V ~ 2.3 V-55 to +100DDR2 SDRAMUnitsV

V

V

V

Notes1111°C 1, 2Note :1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2

standard.9.0 AC & DC Operating Conditions9.1 Recommended DC Operating Conditions (SSTL - 1.8)SymbolVDDVDDLVDDQVREFVTTSupply VoltageSupply Voltage for DLLSupply Voltage for OutputInput Reference VoltageTermination VoltageParameterRatingMin.1.71.71.70.49*VDDQVREF-0.04Typ.

1.81.81.80.50*VDDQVREFMax.1.91.91.90.51*VDDQVREF+0.04UnitsVVVmVV441,23NotesSymbolVDDSPDParameterCore Supply VoltageRatingMin.1.7Max.3.6UnitsVNotes5Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal

to VDD.

1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5

x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).3. VTT of transmitting device must track VREF of receiving device.4. AC parameters are measured with VDD, VDDQ and VDDL tied together.5. SODIMMs that include an optional temperature sensor may require a restricted VDDSPD operating voltage range for proper operation of the temperature

sensor. Refer to the thermal sensor specification for details regarding the supported voltage range. All other functions of the SODIMM SPD are supported

across the full VDDSPD range.

10 of 19Rev. 1.1 July 2008

SODIMM9.2 Operating Temperature ConditionSymbolTOPERParameterOperating TemperatureRating0 to 95UnitsDDR2 SDRAMNotes°C 1, 2Note :

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to

JESD51.2 standard.

2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self

refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.9.3 Input DC Logic LevelSymbolVIH(DC)VIL(DC)ParameterDC input logic high

DC input logic + 0.125- + 0.3VREF - 0.125UnitsVVNotes9.4 Input AC Logic LevelSymbolVIH(AC)VIL(AC)ParameterAC input logic high

AC input logic lowDDR2-667, + 0.200VREF - V9.5 AC Input Test Conditions

SymbolVREFVSWING(MAX)SLEWConditionInput reference voltageInput signal maximum peak to peak swingInput signal minimum slew rateValue0.5 * VDDQ1.01.0UnitsVVV/nsNotes112, 3Note:

1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC)

level applied to the device under test.

2. The input signal minimum slew rate is to be maintained over the range from VREF

to VIH(AC) min for rising edges and the range from VREF to VIL(AC)max for falling edges as shown in the below figure.3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the H(AC) minVSWING(MAX)VIH(DC) minVREFVIL(DC) maxVIL(AC) maxdelta TFVREF - VIL(AC) maxFalling Slew =

delta TFdelta TRVSSVIH(AC) min - VREFRising Slew =

delta TR< AC Input Test Signal Waveform > 11 of 19Rev. 1.1 July 2008

SODIMM10.0 IDD Specification Parameters Definition(IDD values are for full operating range of Voltage and Temperature)SymbolIDD0Proposed ConditionsDDR2 SDRAMUnitsmANoteOperating one bank active-precharge current;

tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHINGOperating one bank active-read-precharge current;IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =

tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern

is same as IDD4WPrecharge power-down current;All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATINGPrecharge quiet standby current;All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data

bus inputs are FLOATINGPrecharge standby current;

All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHINGActive power-down current;All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address

bus inputs are STABLE; Data bus inputs are FLOATINGFast PDN Exit MRS(12) = 0Slow PDN Exit MRS(12) = 1IDD1mAIDD2PmAIDD2QmAIDD2NmAmAmAmAIDD3PIDD3NActive standby current;

All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHINGOperating burst write current;All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP

= tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus

inputs are SWITCHINGOperating burst read current;All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCH-ING; Data pattern is same as IDD4WBurst auto refresh current;

tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands;

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHINGSelf refresh current;

CK and CK at 0V; CKE

≤ 0.2V; Other control and address bus inputs are

FLOATING; Data bus inputs are FLOATINGNormalLow PowerIDD4WmAIDD4RmAIDD5BmAmAmAIDD6IDD7Operating bank interleave read current;All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =

tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid com-mands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following

page for detailed timing conditionsmA 12 of 19Rev. 1.1 July 2008

SODIMM11.0 Operating Current Table :11.1 M470T5663QZ(H)3 : 256Mx64 2GB ModuleSymbolCE7IDD0IDD1IDD2PIDD2QIDD2NIDD3P-FIDD3P-SIDD3NIDD4WIDD4RIDD5IDD6IDD72402,2802887201,2001,3601,4401282402,2887201,2001,3601,4401282402,120800@CL=5LE7CF78801,1201,2401,400128800@CL=6LF7CE684@CL=5LE6DDR2 SDRAM(TA=0oC, VDD= 1.9V)UnitsmAmAmAmAmAmAmAmAmAmAmAmAmANotes* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.11.2 M470T2864QZ(H)3 : 128Mx64 1GB ModuleSymbolIDD0IDD1IDD2PIDD2QIDD2NIDD3P-FIDD3P-SIDD3NIDD4WIDD4RIDD5IDD6IDD71201,28,200800@CL=5CE751201,120LE7CF75800@CL=6LF7CE648052064667@CL=5LE6(TA=0oC, VDD= 1.9V)UnitsmAmAmAmAmAmAmAmAmAmAmAmAmANotes* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.11.3 M470T6464QZ(H)3: 64Mx64 512MB ModuleSymbolIDD0IDD1IDD2PIDD2QIDD2NIDD3P-FIDD3P-SIDD3NIDD4WIDD4RIDD5IDD6IDD7601,458032601,060800@CL=5CE73647LE7CF736462056032800@CL=6LF7CE634038032667@CL=5LE6(TA=0oC, VDD= 1.9V)UnitsmAmAmAmAmAmAmAmAmAmAmAmAmANotes* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 13 of 19Rev. 1.1 July 2008

SODIMM12.0 Input/Output CapacitanceParameterNon-ECCInput capacitance, CK and CKInput capacitance, CKE , CS, Addr, RAS, CAS, WEInput/output capacitance, DQ, DM, DQS, DQS* DM is internally loaded to match DQ and DQS CCKCICIOMin---Max48429Min---Max32349M470T5663QZ(H)3M470T2864QZ(H)3DDR2 SDRAM(VDD=1.8V, VDDQ=1.8V, TA=25oC)Min---Max24345.5pFUnitsM470T6464QZ(H)313.0 Electrical Characteristics & AC Timing for DDR2-800/667(0 °C < TOPER

< 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)13.1 Refresh Parameters by Device DensityParameterRefresh to active/Refresh command timeAverage periodic refresh interval tRFCtREFI0 °C ≤ TCASE

≤ 85°C85 °C < TCASE

≤ 95°CSymbol256Mb757.83.9512Mb1057.83.91Gb127.57.83.92Gb1957.83.94Gb327.57.83.9Unitsnsµsµs13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding BinSpeedBin(CL - tRCD - tRP)ParametertCK, CL=3tCK, CL=4tCK, CL=5tCK, CL=6tRCDtRPtRCtRASmin53.752.5-12.512.557.545DDR2-800(E7)5 - 5 - 5max888----70000DDR2-800(F7)6 - 6- 6min-3.7532.515156045max-888---70000DDR2-667(E6)5 - 5 - 5min53.753-15156045max888----70000Unitsnsnsnsnsnsnsnsns 14 of 19Rev. 1.1 July 2008

SODIMM13.3 Timing Parameters by Speed Grade(Refer to notes for informations related to this table at the component datasheet)ParameterDQ output access time from CK/CKDQS output access time from CK/CKAverage clock HIGH pulse widthAverage clock LOW pulse widthCK half pulse periodAverage clock periodDQ and DM input hold timeDQ and DM input setup timeControl & Address input pulse width for each inputDQ and DM input pulse width for each inputData-out high-impedance time from CK/CKDQS/DQS low-impedance time from CK/CKDQ low-impedance time from CK/CKDQS-DQ skew for DQS and associated DQ signalsDQ hold skew factorDQ/DQS output hold time from DQSDQS latching rising transitions to associated clock edgesDQS input HIGH pulse widthDQS input LOW pulse widthDQS falling edge to CK setup timeDQS falling edge hold time from CKMode register set command cycle timeMRS command to ODT update delayWrite postambleWrite preambleAddress and control input hold timeAddress and control input setup timeRead preambleRead postambleDDR2 SDRAMSymboltACtDQSCKtCH(avg)tCL(avg)tHPtCK(avg)tDH(base)tDS(base)tIPWtDIPWtHZtLZ(DQS)tLZ(DQ)tDQSQtQHStQHtDQSStDQSHtDQSLtDSStDSHtMRDtMODtWPSTtWPREtIH(base)tIS(base)tRPREtRPSTDDR2-800min-400-3500.480.48Min(tCL(abs),tCH(abs))2500125500.60.35xtAC(min)2*tAC(min)xxtHP - tQHS- 0.250.350.350.20.2200.40.352501750.90.47.510DDR2-667min- 450- 4000.480.48Min(tCL(abs),tCH(abs))3.60.35xtAC(min)2*tAC(min)xxtHP - tQHS-0.250.350.350.20.2200.40.352752000.90.47.510max4003500.520.52x8000xxxxtAC(max)tAC(max)tAC(max)200300x0.25xxxxx120.6xxx1.10.6xxmax4504000.520.52x8000xxxxtAC(max)tAC(max)tAC(max)240340x0.25xxxxx120.6xxx1.10.6xxUnitspspstCK(avg)tCK(avg)pspspspstCK(avg)tCK(avg)pspspspspspstCK(avg)tCK(avg)tCK(avg)tCK(avg)tCK(avg)nCKnstCK(avg)tCK(avg)pspstCK(avg)tCK(avg)nsnsNotes404035,3635,363735,366,7,8,21,28,316,7,8,20,28,3118,4018,4018,4032105,7,9,23,295,7,9,22,2919,4119,424,324,32Activate to activate command period for 1KB page size productstRRDActivate to activate command period for 2KB page size productstRRD 15 of 19Rev. 1.1 July 2008

SODIMMDDR2-800min3545215WR + tnRP7.57.5tRFC + 10200228 - AL32tAC(min)tAC(min)+22.5tAC(min)tAC(min)+2380tIS+tCK(avg)+tIHDDR2 SDRAMDDR2-667min37.550215WR + tnRP7.57.5tRFC + 10200227 - AL32tAC(min)tAC(min)+22.5tAC(min)tAC(min)+2380tIS+tCK(avg)+tIHParameterFour Activate Window for 1KB page size productsFour Activate Window for 2KB page size productsCAS to CAS command delayWrite recovery timeAuto precharge write recovery + precharge timeInternal write to read command delayInternal read to precharge command delayExit self refresh to a non-read commandExit self refresh to a read commandExit precharge power down to any commandExit active power down to read commandExit active power down to read command(slow exit, lower power)CKE minimum pulse width (HIGH and LOW pulse width)ODT turn-on delayODT turn-on

ODT turn-on (Power-Down mode)ODT turn-off delayODT turn-offODT turn-off (Power-Down mode)ODT to power down entry latencyODT power down exit latencyOCD drive mode output delaySymboltFAWtFAWtCCDtWRtDALtWTRtRTPtXSNRtXSRDtXPtXARDtXARDStCKEtAONDtAONtAONPDtAOFDtAOFtAOFPDtANPDtAXPDtOITmaxxxxxxxxxxxxxx2tAC(max)+0.72*tCK(avg)+tAC(max)+12.5tAC(max)+0.62.5*tCK(avg)+tAC(max)+1xx12xmaxxxxxxxxxxxxxx2tAC(max)+0.72*tCK(avg)+tAC(max)+12.5tAC(max)+0.62.5*tCK(avg)+tAC(max)+1xx12xUnitsnsnsnCKnsnCKnsnsnsnCKnCKnCKnCKnCKnCKnsnsnCKnsnsnCKnCKnsnsNotes3232323324,323,323211,227166,16,4017,4517,43,453215Minimum time clocks remains ON after CKE asynchronouslytDelaydrops LOW 16 of 19Rev. 1.1 July 2008

SODIMM14.0 Physical Dimensions :14.1 128Mbx8 based 256Mx64 Module (2 Rank)

- M470T5663QZ(H)3DDR2 SDRAMUnits : Millimeters67.60

±

0.15 mmmin 2.0030.00

±

0.15

mmSPD3.8 mmmax6.00

±

0.15

mm111.40

±

0.15 mm16.25

±

0.15 mmab47.40

±

0.15 mm63.00

±

0.15 mm1994.00

±

0.1020.00

±

0.15

mm1.1mmmax2a20030.00

±

0.15

mm67.60

±

0.15 mmDETAIL aDETAIL bFRONT SIDE4.20

±

0.15

2.70 ±

0.101.50 ±

0.10BACK SIDE4.00 ±

0.101.0 ±

0.050.20

±

0.152.55

±

0.151.80 ±

0.104.00 ±

0.101.0 ±

0.054.20

±

0.152.40 ±

0.100.60

±

0.150.45 ±

0.03The used device is 128M x8 DDR2 SDRAM, 2 SDRAM Part NO : K4T1G084QQ 17 of 19Rev. 1.1 July 2008

SODIMMDDR2 SDRAM14.2 64Mbx16 based 128Mx64 Module (2 Rank)

- M470T2864QZ(H)367.60 ±

0.15 mmmin 2.0030.00

±

0.15

mm6.00

±

0.15

mmUnits : Millimeters3.8 mmMax111.40

±

0.15 mm16.25

±

0.15 mmab47.40

±

0.15 mm63.00

±

0.15 mm1994.00

±

0.1020.00

±

0.15

mm1.1 mmMax2aSPD20030.00

±

0.15

mm67.60

±

0.15 mmDETAIL aDETAIL bFRONT SIDE4.20

±

0.15

2.70 ±

0.101.50 ±

0.10BACK SIDE4.00 ±

0.101.0 ±

0.050.20

±

0.152.55

±

0.151.80 ±

0.104.00 ±

0.101.0 ±

0.054.20

±

0.152.40 ±

0.100.60

±

0.150.45 ±

0.03The used device is 64M x16 DDR2 SDRAM, 2 SDRAM Part NO : K4T1G164QQ 18 of 19Rev. 1.1 July 2008

SODIMMDDR2 SDRAM14.3 64Mbx16 based 64Mx64 Module (1 Rank)

- M470T6464QZ(H)367.60

±

0.15 mmmin 2.0030.00

±

0.15

mm6.00

±

0.15

mmUnits : Millimeters3.8 mmMax111.40

±

0.15 mm16.25

±

0.15 mmab47.40

±

0.15 mm63.00

±

0.15 mm19920.00

±

0.15

mm4.00

±

0.10SPD1.1 mmMax2a20030.00

±

0.15

mm67.60

±

0.15 mmDETAIL aDETAIL bFRONT SIDE4.20

±

0.15

2.70 ±

0.101.50 ±

0.10BACK SIDE4.00 ±

0.101.0 ±

0.050.20

±

0.152.55

±

0.151.80 ±

0.104.00 ±

0.101.0 ±

0.054.20

±

0.152.40 ±

0.100.60

±

0.150.45 ±

0.03The used device is 64M x16 DDR2 SDRAM, 2 SDRAM Part NO : K4T1G164QQ 19 of 19Rev. 1.1 July 2008