2024年2月12日发(作者：奥迪迷你mini新款女士)
Samsung Exynos 4 Quad
(Exynos 4412)
RISC Microprocessor
Revision 1.00
October 2012
User's Manual
2012 Samsung Electronics Co., Ltd. All rights reserved.
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Trademarks
All brand names, trademarks and registered trademarks belong to their respective owners.
Exynos, Exynos4412, FlexOneNAND, and OneNAND are trademarks of Samsung Electronics.
ARM, Jazelle, TrustZone, and Thumb are registered trademarks of ARM Limited.
Cortex, ETM, ETB, Coresight, ISA, and Neon are trademarks of ARM Limited.
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Chip Handling Guide
Precaution against Electrostatic Discharge
When using semiconductor devices, ensure that the environment is protected against static electricity:
1. Wear antistatic clothes and use earth band.
2. All objects that are in direct contact with devices must be made up of materials that do not produce static
electricity.
3. Ensure that the equipment and work table are earthed.
4. Use ionizer to remove electron charge.
Contamination
Do not use semiconductor products in an environment exposed to dust or dirt adhesion.
Temperature/Humidity
Semiconductor devices are sensitive to:
Environment
Temperature
Humidity
High temperature or humidity deteriorates the characteristics of semiconductor devices. Therefore, do not store or
use semiconductor devices in such conditions.
Mechanical Shock
Do not to apply excessive mechanical shock or force on semiconductor devices.
Chemical
Do not expose semiconductor devices to chemicals because exposure to chemicals leads to reactions that
deteriorate the characteristics of the devices.
Light Protection
In non- Epoxy Molding Compound (EMC) package, do not expose semiconductor IC to bright light. Exposure to
bright light causes malfunctioning of the devices. However, a few special products that utilize light or with security
functions are exempted from this guide.
Radioactive, Cosmic and X-ray
Radioactive substances, cosmic ray, or X-ray may influence semiconductor devices. These substances or rays
may cause a soft error during a device operation. Therefore, ensure to shield the semiconductor devices under
environment that may be exposed to radioactive substances, cosmic ray, or X-ray.
EMS (Electromagnetic Susceptibility)
Strong electromagnetic wave or magnetic field may affect the characteristic of semiconductor devices during the
operation under insufficient PCB circuit design for Electromagnetic Susceptibility (EMS).
Revision History
Revision No. Date Description
1.00 Aug. 22, 2011
Author(s)
Revision Descriptions for Revision 1.00
Chapter Name Page
01_Product Overview
1-1
1-2
Major Changes comparing with Last Version
Table of Contents
1 PRODUCT OVERVIEW ................................................................................. 1-1
1.1 Introduction .............................................................................................................................................. 1-1
1.2 Features ................................................................................................................................................... 1-2
1.2.1 Multi-Core Processing Unit ............................................................................................................... 1-4
1.2.2 Memory Subsystem .......................................................................................................................... 1-5
1.2.3 Multimedia ........................................................................................................................................ 1-6
1.2.4 Audio Subsystem .............................................................................................................................. 1-8
1.2.5 Image Signal Processing Subsystem ............................................................................................... 1-8
1.2.6 Connectivity ...................................................................................................................................... 1-9
1.2.7 System Peripheral .......................................................................................................................... 1-11
1.3 Conventions ........................................................................................................................................... 1-13
1.3.1 Register RW Conventions .............................................................................................................. 1-13
1.3.2 Register Value Conventions ........................................................................................................... 1-13
2 MEMORY MAP .............................................................................................. 2-1
2.1 Overview .................................................................................................................................................. 2-1
2.2 SFR Base Address .................................................................................................................................. 2-2
3 CHIP ID .......................................................................................................... 3-1
3.1 Overview .................................................................................................................................................. 3-1
3.2 Register Description ................................................................................................................................. 3-2
3.2.1 Register Map Summary .................................................................................................................... 3-2
4 GENERAL PURPOSE INPUT/OUTPUT (GPIO) CONTROL ......................... 4-1
4.1 Overview .................................................................................................................................................. 4-1
4.2 Features ................................................................................................................................................... 4-3
4.2.1 Input/Output Description ................................................................................................................... 4-3
4.3 Register Description ................................................................................................................................. 4-5
4.3.1 Registers Summary .......................................................................................................................... 4-5
4.3.2 Part 1 .............................................................................................................................................. 4-20
4.3.3 Part 2 ............................................................................................................................................ 4-124
4.3.4 Part 3 ............................................................................................................................................ 4-289
4.3.5 Part 4 ............................................................................................................................................ 4-298
5 CLOCK MANAGEMENT UNIT ...................................................................... 5-1
5.1 Overview .................................................................................................................................................. 5-1
5.2 Clock Domains ......................................................................................................................................... 5-1
5.3 Clock Declaration ..................................................................................................................................... 5-3
5.3.1 Clocks from Clock Pads ................................................................................................................... 5-3
5.3.2 Clocks from CMU .............................................................................................................................. 5-4
5.4 Clock Relationship ................................................................................................................................... 5-5
5.4.1 Recommended PLL PMS Value for APLL and MPLL ...................................................................... 5-7
5.4.2 Recommended PLL PMS Value for EPLL ........................................................................................ 5-8
5.4.3 Recommended PLL PMS Value for VPLL ........................................................................................ 5-9
5.5 Clock Generation ................................................................................................................................... 5-10
5.6 Clock Configuration Procedure .............................................................................................................. 5-15
5.6.1 Clock Gating ................................................................................................................................... 5-16
5.6.2 Clock Diving .................................................................................................................................... 5-16
5.7 Special Clock Description ...................................................................................................................... 5-17
5.7.1 Special Clock Table ........................................................................................................................ 5-17
5.8 CLKOUT ................................................................................................................................................. 5-20
5.9 I/O Description ....................................................................................................................................... 5-23
5.10 Register Description ............................................................................................................................. 5-24
5.10.1 Register Map Summary ................................................................................................................ 5-26
6 INTERRUPT CONTROLLER ......................................................................... 6-1
6.1 Overview .................................................................................................................................................. 6-1
6.2 Features ................................................................................................................................................... 6-2
6.2.1 Security Extensions Support ............................................................................................................ 6-2
6.2.2 Implementation-Specific Configurable Features .............................................................................. 6-3
6.3 Interrupt Source ....................................................................................................................................... 6-4
6.3.1 Interrupt Sources Connection ........................................................................................................... 6-4
6.3.2 GIC Interrupt Table ........................................................................................................................... 6-5
6.4 Functional Overview .............................................................................................................................. 6-13
6.5 Register Description ............................................................................................................................... 6-14
6.5.1 Register Map Summary .................................................................................................................. 6-14
7 INTERRUPT COMBINER .............................................................................. 7-1
7.1 Overview .................................................................................................................................................. 7-1
7.2 Features ................................................................................................................................................... 7-1
7.3 Functional Description ............................................................................................................................. 7-2
7.3.1 Block Diagram .................................................................................................................................. 7-2
7.4 7-3
7.4.1 Interrupt Combiner ............................................................................................................................ 7-3
7.5 Functional Description ............................................................................................................................. 7-8
7.6 Register Description ................................................................................................................................. 7-9
7.6.1 Register Map Summary .................................................................................................................... 7-9
7.6.2 Interrupt Combiner .......................................................................................................................... 7-10
8 DIRECT MEMORY ACCESS CONTROLLER (DMAC) ................................. 8-1
8.1 Overview .................................................................................................................................................. 8-1
8.2 Features ................................................................................................................................................... 8-2
8.3 Register Description ................................................................................................................................. 8-5
8.3.1 Register Map Summary .................................................................................................................... 8-5
8.4 Instruction ............................................................................................................................................... 8-14
9 SROM CONTROLLER ................................................................................... 9-1
9.1 Overview .................................................................................................................................................. 9-1
9.2 Features ................................................................................................................................................... 9-1
9.3 Block Diagram .......................................................................................................................................... 9-1
9.4 Functional Description ............................................................................................................................. 9-2
9.4.1 nWAIT Pin Operation ........................................................................................................................ 9-2
9.4.2 Programmable Access Cycle ........................................................................................................... 9-3
9.5 I/O Description ......................................................................................................................................... 9-4
9.6 Register Description ................................................................................................................................. 9-5
9.6.1 Register Map Summary .................................................................................................................... 9-5
10 NAND FLASH CONTROLLER .................................................................. 10-1
10.1 Overview .............................................................................................................................................. 10-1
10.2 Features ............................................................................................................................................... 10-1
10.3 Functional Description ......................................................................................................................... 10-2
10.3.1 Block Diagram .............................................................................................................................. 10-2
10.3.2 NAND Flash Memory Timing ........................................................................................................ 10-3
10.4 Software Mode ..................................................................................................................................... 10-4
10.4.1 Data Register Configuration ......................................................................................................... 10-4
10.4.2 1/4/8/12/16-bit ECC ...................................................................................................................... 10-5
10.4.3 2048 Byte 1-bit ECC Parity Code Assignment Table ................................................................... 10-6
10.4.4 32 Byte 1-bit ECC Parity Code Assignment Table ....................................................................... 10-6
10.4.5 1-bit ECC Module Features .......................................................................................................... 10-6
10.4.6 1-bit ECC Programming Guide ..................................................................................................... 10-7
10.4.7 4-bit ECC Programming Guide (ENCODING) .............................................................................. 10-8
10.4.8 4-bit ECC Programming Guide (DECODING) .............................................................................. 10-9
10.4.9 8/12/16-bit ECC Programming Guide (ENCODING) .................................................................. 10-10
10.4.10 8/12/16-bit ECC Programming Guide (DECODING) ................................................................ 10-11
10.4.11 ECC Parity Conversion Code Guide for 8/12/16-bit ECC ........................................................ 10-12
10.4.12 Lock Scheme for Data Protection ............................................................................................. 10-13
10.5 Programming Constraints .................................................................................................................. 10-14
10.6 I/O Description ................................................................................................................................... 10-14
10.7 Register Description ........................................................................................................................... 10-15
10.7.1 Register Map Summary .............................................................................................................. 10-15
10.7.2 NAND Flash Interface and 1/4-bit ECC Registers ...................................................................... 10-17
10.7.3 ECC Registers for 8, 12 and 16-bit ECC .................................................................................... 10-29
11 PULSE WIDTH MODULATION TIMER ..................................................... 11-1
11.1 Overview .............................................................................................................................................. 11-1
11.2 Features ............................................................................................................................................... 11-4
11.3 11-5
11.3.1 Prescaler and Divider ................................................................................................................... 11-5
11.3.2 Basic Timer Operation .................................................................................................................. 11-6
11.3.3 Auto-Reload and Double Buffering ............................................................................................... 11-8
11.3.4 Timer Operation Example ............................................................................................................. 11-9
11.3.5 Initialize Timer (Setting Manual-Up Data and Inverter) .............................................................. 11-10
11.3.6 PWM ........................................................................................................................................... 11-10
11.3.7 During Current ISR. (Interrupt Service Routine) Output Level Control ...................................... 11-11
11.3.8 Dead Zone Generator ................................................................................................................. 11-12
11.4 I/O Description ................................................................................................................................... 11-13
11.5 Register Description ........................................................................................................................... 11-14
11.5.1 Register Map Summary .............................................................................................................. 11-14
12 WATCHDOG TIMER .................................................................................. 12-1
12.1 Overview .............................................................................................................................................. 12-1
12.2 Features ............................................................................................................................................... 12-1
12.3 Functional Description ......................................................................................................................... 12-2
12.3.1 WDT Operation ............................................................................................................................. 12-2
12.3.2 WTDAT and WTCNT .................................................................................................................... 12-3
12.3.3 WDT Start ..................................................................................................................................... 12-3
12.3.4 Consideration of Debugging Environment .................................................................................... 12-3
12.4 Register Description ............................................................................................................................. 12-4
12.4.1 Register Map Summary ................................................................................................................ 12-4
13 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER ......... 13-1
13.1 Overview .............................................................................................................................................. 13-1
13.2 Features ............................................................................................................................................... 13-0
13.3 UART Description ................................................................................................................................ 13-1
13.3.1 Data Transmission ........................................................................................................................ 13-2
13.3.2 Data Reception ............................................................................................................................. 13-2
13.3.3 AFC ............................................................................................................................................... 13-3
13.3.4 Example of Non AFC (Controlling nRTS and nCTS by Software) ............................................... 13-4
13.3.5 Trigger Level of Tx/Rx FIFO and DMA Burst Size in DMA Mode ................................................ 13-4
13.3.6 RS-232C Interface ........................................................................................................................ 13-4
13.3.7 Interrupt/DMA Request Generation .............................................................................................. 13-5
13.3.8 UART Error Status FIFO .............................................................................................................. 13-7
13.4 UART Input Clock Description ........................................................................................................... 13-10
13.5 I/O Description ................................................................................................................................... 13-11
13.6 Register Description ........................................................................................................................... 13-12
13.6.1 Register Map Summary .............................................................................................................. 13-12
14 INTER-INTEGRATED CIRCUIT ................................................................. 14-1
14.1 Overview .............................................................................................................................................. 14-1
14.2 Features ............................................................................................................................................... 14-2
14.3 Functional Description ......................................................................................................................... 14-2
14.3.1 Block Diagram .............................................................................................................................. 14-2
14.4 I2C-Bus Interface Operation ................................................................................................................ 14-3
14.4.1 Start and Stop Conditions ............................................................................................................. 14-4
14.4.2 Data Transfer Format ................................................................................................................... 14-5
14.4.3 ACK Signal Transmission ............................................................................................................. 14-6
14.4.4 Read-Write Operation ................................................................................................................... 14-7
14.4.5 Bus Arbitration Procedures ........................................................................................................... 14-7
14.4.6 Abort Conditions ........................................................................................................................... 14-7
14.4.7 Configuring I2C-Bus ..................................................................................................................... 14-7
14.4.8 Flowcharts of Operations in Each Mode ...................................................................................... 14-8
14.5 I/O Description ................................................................................................................................... 14-12
14.6 Register Description ........................................................................................................................... 14-13
14.6.1 Register Map Summary .............................................................................................................. 14-13
15 SERIAL PERIPHERAL INTERFACE ......................................................... 15-1
15.1 Overview .............................................................................................................................................. 15-1
15.2 Features ............................................................................................................................................... 15-1
15.2.1 Operation of SPI ........................................................................................................................... 15-2
15.3 SPI Input Clock Description ................................................................................................................. 15-5
15.4 IO Description ...................................................................................................................................... 15-6
15.5 Register Description ............................................................................................................................. 15-7
15.5.1 Register Map Summary ................................................................................................................ 15-7
16 DISPLAY CONTROLLER .......................................................................... 16-1
16.1 Overview .............................................................................................................................................. 16-1
16.2 Features ............................................................................................................................................... 16-2
16.3 Functional Description ......................................................................................................................... 16-4
16.3.1 Brief Description ........................................................................................................................... 16-4
16.3.2 Data Flow ...................................................................................................................................... 16-5
16.3.3 Overview of the Color Data .......................................................................................................... 16-8
16.3.4 Palette Usage ............................................................................................................................. 16-23
16.3.5 Window Blending ........................................................................................................................ 16-26
16.3.6 VTIME Controller Operation ....................................................................................................... 16-35
16.3.7 Virtual Display ............................................................................................................................. 16-39
16.3.8 RGB Interface Specification ....................................................................................................... 16-40
16.3.9 LCD Indirect i80 System Interface .............................................................................................. 16-43
16.4 I/O Description ................................................................................................................................... 16-47
16.5 Register Description ........................................................................................................................... 16-48
16.5.1 Register Map Summary .............................................................................................................. 16-49
16.5.2 Palette Memory ........................................................................................................................... 16-56
16.5.3 Control Register .......................................................................................................................... 16-57
16.5.4 Gamma Lookup Table .............................................................................................................. 16-131
16.5.5 Shadow Windows Control ........................................................................................................ 16-134
16.5.6 Palette Ram .............................................................................................................................. 16-136
17 KEYPAD INTERFACE ............................................................................... 17-1
17.1 Overview .............................................................................................................................................. 17-1
17.2 Debouncing Filter ................................................................................................................................. 17-3
17.3 Filter Clock ........................................................................................................................................... 17-3
17.4 17-3
17.5 Keypad Scanning Procedure for Software Scan ................................................................................. 17-4
17.6 Keypad Scanning Procedure for Hardware Scan ................................................................................ 17-9
17.7 I/O Description ................................................................................................................................... 17-10
17.8 Register Description ........................................................................................................................... 17-12
17.8.1 Register Map Summary .............................................................................................................. 17-12
18 ADC ........................................................................................................... 18-1
18.1 Overview .............................................................................................................................................. 18-1
18.2 Features ............................................................................................................................................... 18-1
18.3 Functional Description ......................................................................................................................... 18-1
18.3.1 Block Diagram .............................................................................................................................. 18-1
18.3.2 ADC Selection .............................................................................................................................. 18-2
18.3.3 A/D 18-2
18.3.4 ADC Conversion Mode ................................................................................................................. 18-2
18.3.5 Standby Mode ............................................................................................................................... 18-3
18.4 ADC Input Clock Diagram .................................................................................................................... 18-4
18.5 I/ 18-5
18.6 Register Description ............................................................................................................................. 18-6
18.6.1 Register Map Summary ................................................................................................................ 18-6
List of Figures
Figure Title Page
Number Number
Figure 4-1 GPIO Block Diagram ........................................................................................................................ 4-4
Figure 5-1 Exynos4412 Clock Generation Circuit (CPU, BUS, DRAM, ISP Clocks) ....................................... 5-12
Figure 5-2 Exynos4412 Clock Generation Circuit (Special Clocks) ................................................................. 5-14
Figure 5-3 Exynos4412 CLKOUT Control Logic .............................................................................................. 5-20
Figure 5-4 Exynos4412 Clock Controller Address Map ................................................................................... 5-25
Figure 6-1 Interrupt Sources Connection ........................................................................................................... 6-4
Figure 7-1 Block Diagram of Interrupt Combiner ............................................................................................... 7-2
Figure 8-1 Two DMA Tops ................................................................................................................................. 8-1
Figure 9-1 Block Diagram of SROMC Introduction ............................................................................................ 9-1
Figure 9-2 SROMC nWAIT Timing Diagram ...................................................................................................... 9-2
Figure 9-3 SROMC Read Timing Diagram ........................................................................................................ 9-3
Figure 9-4 SROMC Write Timing Diagram ......................................................................................................... 9-3
Figure 10-1 NAND Flash Controller Block Diagram ......................................................................................... 10-2
Figure 10-2 CLE and ALE Timing (TACLS = 1, TWRPH0 = 0, TWRPH1 = 0) ................................................ 10-3
Figure 10-3 nWE and nRE Timing (TWRPH0 = 0, TWRPH1 = 0) ................................................................... 10-3
Figure 10-4 Accessibility of NAND Area ........................................................................................................ 10-13
Figure 11-1 Simple Example of a PWM Cycle ................................................................................................. 11-2
Figure 11-2 PWM TIMER Clock Tree Diagram ................................................................................................ 11-3
Figure 11-3 Timer Operations .......................................................................................................................... 11-6
Figure 11-4 Example of Double Buffering Feature .......................................................................................... 11-8
Figure 11-5 Example of a Timer Operation ...................................................................................................... 11-9
Figure 11-6 Example of PWM ........................................................................................................................ 11-10
Figure 11-7 Inverter On/Off ............................................................................................................................ 11-11
Figure 11-8 Waveform when a Dead Zone Feature 11-12
Figure 12-1 Watchdog Timer Block Diagram ................................................................................................... 12-2
Figure 13-1 Block Diagram of UART ................................................................................................................ 13-1
Figure 13-2 UART AFC Interface ..................................................................................................................... 13-3
Figure 13-3 UART Receives the Five Characters Including Two Errors ......................................................... 13-7
Figure 13-4 IrDA Function Block Diagram ....................................................................................................... 13-8
Figure 13-5 Serial I/O Frame Timing Diagram (Normal UART) ....................................................................... 13-8
Figure 13-6 Infra-Red Transmit Mode Frame Timing Diagram ........................................................................ 13-9
Figure 13-7 Infra-Red Receive Mode Frame Timing Diagram ......................................................................... 13-9
Figure 13-8 Input Clock Diagram for UART ................................................................................................... 13-10
Figure 13-9 nCTS and Delta CTS Timing Diagram ....................................................................................... 13-25
Figure 13-10 Block Diagram of UINTSP, UINTP, and UINTM ....................................................................... 13-30
Figure 14-1 I2C-Bus Block Diagram ................................................................................................................ 14-2
Figure 14-2 Start and Stop Condition ............................................................................................................... 14-4
Figure 14-3 I2C-Bus Interface Data Format ..................................................................................................... 14-5
Figure 14-4 Data Transfer on the I2C-Bus ....................................................................................................... 14-5
Figure 14-5 Acknowledgement on the I2C-Bus ............................................................................................... 14-6
Figure 14-6 Operations for Master/Transmitter Mode ...................................................................................... 14-8
Figure 14-7 Operations for Master/Receiver Mode .......................................................................................... 14-9
Figure 14-8 Operations for Slave/Transmitter Mode ...................................................................................... 14-10
Figure 14-9 Operations for Slave/Receiver Mode .......................................................................................... 14-11
Figure 15-1 SPI Transfer Format ..................................................................................................................... 15-4
Figure 15-2 Input Clock Diagram for SPI ......................................................................................................... 15-5
Figure 15-3 Auto Chip Select Mode Waveform (CPOL = 0, CPHA = 0, CH_WIDTH = Byte) ....................... 15-10
Figure 16-1 Block Diagram of Display Controller ............................................................................................. 16-1
Figure 16-2 Block Diagram of the Data Flow ................................................................................................... 16-6
Figure 16-3 Block Diagram of the Interface ..................................................................................................... 16-7
Figure 16-4 Memory Format of 25 BPP(A888) Display ................................................................................... 16-8
Figure 16-5 Memory Format of 32 BPP (8888) Display ................................................................................... 16-9
Figure 16-6 Memory Format of 24 BPP (A887) Display ................................................................................ 16-10
Figure 16-7 Memory Format of 24 BPP (888) Display ................................................................................... 16-11
Figure 16-8 Memory Format of 19 BPP (A666) Display ................................................................................ 16-12
Figure 16-9 Memory Format of 18 BPP (666) Display ................................................................................... 16-13
Figure 16-10 Memory Format of 16 BPP (A555) Display .............................................................................. 16-14
Figure 16-11 Memory Format of 16 BPP (1555) Display ............................................................................... 16-15
Figure 16-12 Memory Format of 16 BPP (565) Display ................................................................................. 16-16
Figure 16-13 16 BPP (5:6:5) 16-17
Figure 16-14 Memory Format of 13 BPP (A444) Display .............................................................................. 16-18
Figure 16-15 Memory Format of 8 BPP (A232) Display ................................................................................ 16-19
Figure 16-16 Memory Format of 8 BPP Display ............................................................................................ 16-20
Figure 16-17 Memory Format of 4 BPP Display ............................................................................................ 16-21
Figure 16-18 Memory Format of 2 BPP Display ............................................................................................ 16-22
Figure 16-19 32 BPP (8:8:8:8) Palette Data Format ...................................................................................... 16-23
Figure 16-20 25 BPP (A: 8:8:8) Palette Data Format .................................................................................... 16-24
Figure 16-21 19 BPP (A: 6:6:6) Palette Data Format .................................................................................... 16-24
Figure 16-22 16 BPP (A: 5:5:5) Palette Data Format .................................................................................... 16-25
Figure 16-23 Blending Equation ..................................................................................................................... 16-28
Figure 16-24 Blending Diagram ..................................................................................................................... 16-30
Figure 16-25 Blending Factor Decision .......................................................................................................... 16-31
Figure 16-26 Color-Key Function Configurations ........................................................................................... 16-32
Figure 16-27 Blending and Color-Key Function ............................................................................................. 16-33
Figure 16-28 Blending Decision Diagram ...................................................................................................... 16-34
Figure 16-29 Example of Scrolling in Virtual Display ..................................................................................... 16-39
Figure 16-30 LCD RGB Interface Timing ....................................................................................................... 16-42
Figure 16-31 Indirect i80 System Interface Write Cycle Timing ..................................................................... 16-45
Figure 17-1 Key Matrix Interface External Connection Guide .......................................................................... 17-2
Figure 17-2 Internal Debouncing Filter Operation ............................................................................................ 17-3
Figure 17-3 Keypad Scanning Procedure ........................................................................................................ 17-4
Figure 17-4 Keypad Scanning Procedure II ..................................................................................................... 17-5
Figure 17-5 Keypad Scanning Procedure III .................................................................................................... 17-6
Figure 17-6 Keypad Scanning Procedure when the Two-key Pressed with Different Row ............................. 17-7
Figure 17-7 Keypad I/F Block Diagram ............................................................................................................ 17-8
Figure 18-1 ADC Top/Bottom Offset Error Diagram ........................................................................................ 18-1
Figure 18-2 ADC Functional Block Diagram .................................................................................................... 18-1
Figure 18-3 18-2
Figure 18-4 Input Clock Diagram for ADC & Touch Screen Interface ............................................................. 18-4
List of Tables
Table Title Page
Number Number
Table 5-1 Operating Frequencies in Exynos4412 .............................................................................................. 5-2
Table 5-2 APLL and MPLL PMS Value .............................................................................................................. 5-7
Table 5-3 EPLL PMS Value ............................................................................................................................... 5-8
Table 5-4 VPLL PMS Value ............................................................................................................................... 5-9
Table 5-5 Special Clocks in Exynos4412 ......................................................................................................... 5-17
Table 5-6 I/O Clocks in Exynos4412 ................................................................................................................ 5-19
Table 5-7 CLKOUT Input Clock Selection Information .................................................................................... 5-21
Table 5-8 I/O Description ................................................................................................................................. 5-23
Table 6-1 GIC Configuration Values .................................................................................................................. 6-3
Table 6-2 GIC Interrupt Table (SPI[127:0]) ........................................................................................................ 6-5
Table 6-3 GIC Interrupt Table (PPI[15:0]) ........................................................................................................ 6-12
Table 7-1 Interrupt Groups of Interrupt Combiner .............................................................................................. 7-3
Table 8-1 Features of DMA Controller ............................................................................................................... 8-2
Table 8-2 DMA Request Mapping Table ............................................................................................................ 8-2
Table 11-1 Minimum and Maximum Resolution Based on Prescaler and Clock Divider Values ..................... 11-5
Table 13-1 Interrupts in Connection with FIFO ................................................................................................ 13-6
Table 16-1 Relation 16 BPP between VCLK and CLKVAL (TFT, Frequency of Video Clock Source = 60 MHz)
.................................................................................................................................................. 16-35
Table 16-2 RGB Interface Signals of Display Controller ................................................................................ 16-40
Table 16-3 LCD Indirect i80 System Interface Signals of Display Controller ................................................. 16-43
Table 16-4 Timing Reference Code (XY Definition) ....................................................................................... 16-46
Table 16-5 I/O Signals of Display Controller .................................................................................................. 16-47
Table 17-1 Keypad Interface I/O Description ................................................................................................. 17-10
List of Examples
Example Title Page
Number Number
Example 16-1 16-26
Example 16-2 Total Five Windows ................................................................................................................. 16-26
Example 16-3 Blending Equation ................................................................................................................... 16-27
Example 16-4 Default Blending Equation ...................................................................................................... 16-28
Example 16-5 Window Blending Factor Decision .......................................................................................... 16-30
Example 16-6 Hue Equation ........................................................................................................................ 16-119
Example 16-7 Coefficient Decision .............................................................................................................. 16-119
List of Conventions
Register RW Access Type Conventions
Type
R
W
RW
Register Value Conventions
Expression
x
X
?
Device dependent
Pin value
Reset Value Conventions
Expression
0
1
x
Clears the register field
Sets the register field
Don't care condition
Description
Undefined bit
Undefined multiple bits
Undefined, but depends on the device or pin status
The value depends on the device
The value depends on the pin status
Description
Definition
Read Only
Write Only
Description
The application has permission to read the Register field. Writes to read-only fields
have no effect.
The application has permission to write in the Register field.
Read & Write The application has permission to read and writes in the Register field. The
application sets this field by writing 1’b1 and clears it by writing 1’b0.
Warning: Some bits of control registers are driven by hardware or write operation only. As a result the indicated
reset value and the read value after reset might be different.
Exynos 4412_UM 1 Product Overview
1
Product Overview
1.1 Introduction
Exynos 4412 is a 32-bit RISC cost-effective, low power, performance optimized and Coretex-A9 Quad Core based
micro-processor solution for smart phone applications.
The memory system has dedicated DRAM ports and Static Memory port. The dedicated DRAM ports support
LPDDR2 interface for high bandwidth. Static Memory Port supports NOR Flash and ROM type external memory
and components.
To reduce the total system cost and enhance the overall functionality, Exynos 4412 includes many hardware
peripherals, such as TFT 24-bit true color LCD controller, Camera Interface, MIPI DSI, CSI-2, System Manager for
power management, MIPI slimbus interface, MIPI HSI, four UARTs, 24-channel DMA, Timers, General I/O Ports,
three I2S, S/PDIF, eight IIC-BUS interface, three HS-SPI, USB Host 2.0, USB 2.0 Device operating at high speed
(480 Mbps), two USB HSIC, four SD Host and high-speed Multimedia Card Interface, Chip to Chip interface, and
four PLLs for clock generation.
1-1
Exynos 4412_UM 1 Product Overview
1.2 Features
The features of Exynos 4412 are:
ARM Cortex-A9 based Quad CPU Subsystem with NEON
32/32/32/32 KB I/D Cache, 1 MB L2 Cache
Operating frequency up to 800 MHz at 0.9 V, 1 GHz at 1.0 V, and 1.4 GHz at TBD V
128-bit/64-bit Multi-layer bus architecture
Core-D domain for ARM Cortex-A9 Quad, CoreSight, and external memory interface
Operating frequency up to 200 MHz at 1.0 V
Global D- domain mainly for multimedia components and external storage interfaces
Operating frequency up to 100 MHz at 1.0 V
Core-P, Global-P domain mainly for other system component, such as system peripherals, peripheral
DMAs, connectivity IPs and Audio interfaces.
Operating frequency up to 100 MHz at 1.0 V
Audio domain for low power audio play
Advanced power management for mobile applications
64 KB ROM for secure booting and 256 KB RAM for security function
8-bit ITU 601/656 Camera Interface supports horizontal size up to 4224 pixels for scaled and 8192 pixels for
un-scaled resolution
2D Graphics Acceleration support.
1/2/4/ 8bpp Palletized or 8/16/24bpp Non-Palletized Color TFT recommend up to WXGA resolution
HDMI interface support for NTSC and PAL mode with image enhancer
MIPI-DSI and MIPI-CSI interface support
One AC-97 audio codec interface and 3-channel PCM serial audio interface
Three 24-bit I2S interface support
One TX only S/PDIF interface support for digital audio
Eight I2C interface support
Three SPI support
Four UART supports three Mbps ports for Bluetooth 2.0
On-chip USB 2.0 Device supports high-speed (480 Mbps, on-chip transceiver)
On-chip USB 2.0 Host support
Two on-chip USB HSIC
Four SD/ SDIO/HS-MMC interface support
1-2
Exynos 4412_UM 1 Product Overview
24-channel DMA controller (8 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA)
Supports 14 8 key matrix
Configurable GPIOs
Real time clock, PLL, timer with PWM, and watch dog timer
Multi-core timer support for accurate tick time in power down mode (except sleep mode)
Memory Subsystem
Asynchronous SRAM/ ROM/NOR interface with x8 or x16 data bus
NAND interface with x8 data bus
LPDDR2 interface (800 Mbps/pin DDR)
1-3
Exynos 4412_UM 1 Product Overview
1.2.1 Multi-Core Processing Unit
The features of main microprocessors are:
The ARM Cortex-A9 MPCore (quad core) processor integrates the proven and highly successful ARM
MPCore technology along with further enhancements to simplify and broaden the adoption of multi-core
solutions.
With the ability to scale in speed from 200 MHz to 1.4 GHz (TBD), the ARM Cortex-A9 MPCore quad
processor meets the requirements of power-optimized mobile devices, which require operation in low power
and performance-optimized consumer applications. They require over 2000 Dhrystone MIPS.
Other features of ARM Cortex-A9 MPCore quad core processor are:
Thumb-2 technology for greater performance, energy efficiency, and code density
NEONTM signal processing extensions
Jazelle RCT Java-acceleration technology
TrustZone technology for secure transactions and DRM
Floating-Point unit for significant acceleration for both single and double precision scalar Floating-Point
operations
Optimized L1 caches for performance and power
Integrated 1 MB L2 Cache using standard compiled RAMs
Program Trace Macrocell and CoreSight
Generic Interrupt Controller
Supports three interrupt types
o Software Generated Interrupt (SGI)
o Private Peripheral Interrupt (PPI)
o Shared Peripheral Interrupt (SPI)
Programmable interrupts that enable to set the
o Security state for an interrupt
o Priority level of an interrupt
o Enabling or disabling of an interrupt
o Processors that receive an interrupt
Enhanced security features
1-4
Exynos 4412_UM 1 Product Overview
1.2.2 Memory Subsystem
The features of memory subsystem are:
High bandwidth Memory Matrix subsystem
Two independent external memory ports:
o 1x16 Static Hybrid Memory port
o 2x32 DRAM port
Matrix architecture increases the overall bandwidth with simultaneous access capability:
SRAM/ROM/NOR Interface
o x8 or x16 data bus
o Addresses range support: 23-bit
o Supports asynchronous interface
o Supports byte and half-word access
NAND Interface
o Supports industry standard NAND interface
o x8 data bus
LPDDR2 interface
o x32 data bus up to 800 Mbps/pin
o 1.2 V interface voltage
o Density support up to 4-Gb per port (2CS)
1-5
Exynos 4412_UM 1 Product Overview
1.2.3 Multimedia
The features of multimedia are:
Camera Interface
Multiple input support
o ITU-R BT 601/656 mode
o DMA (AXI 64-bit interface) mode
o MIPI (CSI) mode
o Direct FIFO mode (from LCDC)
Multiple output support
o DMA (AXI 64-bit interface) mode
o Direct FIFO mode (to LCDC)
Digital Zoom In (DZI) capability
Multiple camera input support
Programmable polarity of video sync signals
Input horizontal size support up to 4224 pixels for scaled and 8192 pixels for un-scaled resolution
Image mirror and rotation (X-axis mirror, Y-axis mirror, 90, 180, and 270 rotation)
Various image formats generation
Capture frame control support
Image effect support
JPEG Codec supports:
Compression/Decompression up to 65536 65536
Supported format of compression
o Input raw image: YCbCr4:2:2 or RGB 565
o Output JPEG file: Baseline JPEG of YCbCr4:2:2 or YCbCr4:2:0
General-purpose color-space converter
2D Graphic Engine supports:
BitBLT
Maximum 8000 8000 image size
Window clipping, 90/180/270/Rotation, X Flip/Y Flip
Totally 4-operand raster operation (ROP4)
Alpha blending (user-specified constant alpha value/per-pixel alpha value)
8/16/24/32-bpp. Packed 24-bpp color format, Premultiplied/Non-premultiplied alpha format
1 bpp/4 bpp/8 bpp/16 bpp/32 bpp Mask format, YCbCr format
1-6
Exynos 4412_UM 1 Product Overview
Digital TV Interface supports:
High-Definition Multimedia Interface (HDMI) 1.4 a
Up to 1080 p 60 Hz and 8-channel/112 kHz/24-bit audio
480 p, 576 p, 720 p, 1080i (cannot support 480i)
HDCP V1.1
3D support
Rotator
Supported image format: YCbCr422 (Interleave), YCbCr420 (Non-interleave), and RGB565 and RGB888
(unpacked)
Supported rotate degree: 90, 180, 270, flip vertical, and flip horizontal
Video processor: The video processor supports:
BOB/2D-IPC mode
Production of YCbCr 4: 4: 4 output to help the mixer blend video and graphics
1/4X to 16X vertical scaling with 4-tap/16-phase polyphase filter
1/4X to 16X horizontal scaling with 8-tap/16-phase polyphase filter
Pan and scan, Letterbox, and NTSC/PAL conversion using scaling
Flexible scaled video positioning within display area
1/16 pixel resolution Pan and Scan modes
Flexible post video processing
o Color saturation, brightness/contrast enhancement, edge enhancement
o Color space conversion between BT.601 and BT.709
Video input source size up to 1920 1080
Video Mixer
The Video Mixer supports:
Overlapping and blending input video and graphic layers
480p, 576p, 720p, and 1080i/p display size
Four layers (1 video layer, 2 graphic layer, and 1 background layer)
TFT-LCD Interface
The TFT-LCD Interface supports:
24/18/16-bpp parallel RGB Interface LCD
8/6 bpp serial RGB Interface
Dual i80 Interface LCD
1/2/4/8 bpp Palletized or 8/16/24-bpp Non-Palletized Color TFT
Typical actual screen size: 1080 1024,1024 768, 800 480, 640 480, 320 240, 160 160,
and so on
Virtual image up to 16M pixel (4K pixel 4K pixel)
Five Window Layers for PIP or OSD
Real-time overlay plane multiplexing
Programmable OSD window positioning
16-level alpha blending
1-7
Exynos 4412_UM 1 Product Overview
1.2.4 Audio Subsystem
The features of audio subsystem are:
Reconfigurable Processor (RP) progresses audio processing
Low power audio subsystem
5.1 channel I2S with 32-bit-width 64-depth FIFO
128 KB audio play output buffer
Hardware mixer mixes primary and secondary sounds
1.2.5 Image Signal Processing Subsystem
The features of ISP subsystem are:
Dual camera input
Image signal processing
Dynamic range correction
Face detection
1-8
Exynos 4412_UM 1 Product Overview
1.2.6 Connectivity
The features of connectivity are:
PCM Audio Interface supports:
16-bit mono audio interface
Master mode only
3-port PCM interface
AC97 Audio Interface supports:
Independent channels for stereo PCM In, stereo PCM Out, and mono MIC In
16-bit stereo (2-channel) audio
Variable sampling rate AC97 Codec interface (48 kHz and below)
AC97 full specification
SPDIF Interface (TX only) supports:
Linear PCM up to 24-bit per sample support
Non-Linear PCM formats such as AC3, MPEG1, and MPEG2 support
2x24-bit buffers that are alternately filled with data
I2S Bus Interface supports:
Three I2S-bus for audio-codec interface with DMA-based operation
Serial and 8/16/24-bit per channel data transfers
I2S, MSB-justified, and LSB-justified data format
PCM 5.1 channel
Various bit clock frequency and codec clock frequency support
o 16, 24, 32, and 48fs of bit clock frequency
o 256, 384, 512, and 768fs of codec clock
One port for 5.1 channel I2S (in audio subsystem) and two ports for 2-channel I2S
I2C Bus Interface supports:
Eight Multi-Master IIC-Bus
Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbps in the standard
mode
Up to 400 Kbps in the fast mode
MIPI-Slim bus Interface supports:
6 ports. Each port has 16 entry FIFO with 32-bit width
UART supports:
Four UART with DMA-based or interrupt-based operation
5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/ receive
Rx/Tx independent 256nbyte FIFO for UART0, 64 byte FIFO for UART1, and 16 byte FIFO for UART2/3/4
Programmable baud rate
IrDA 1.0 SIR (115.2 Kbps) mode
Loop back mode for testing
Non-integer clock divides in Baud clock generation
1-9
Exynos 4412_UM 1 Product Overview
USB 2.0 Device supports:
Complies to USB 2.0 Specification (Revision 1.0a) High-speed up to 480 Mbps
On-chip USB transceiver
USB Host 2.0 supports:
With the USB Host 2.0
High-speed up to 480 Mbps
On-chip USB transceiver
HS-MMC/SDIO Interface supports:
Multimedia Card Protocol version 4.3 compatible (HS-MMC)
SD Memory Card Protocol version 2.0 compatible
DMA based or interrupt based operation
128 word FIFO for Tx/Rx
Four ports HS-MMC or four ports SDIO
SPI Interface supports:
With three Serial Peripheral Interface Protocol version 2.11
Rx/Tx independent 64-Word FIFO for SPI0 and 16-Word FIFO for SPI1
DMA-based or interrupt-based operation
Chip to Chip Interface supports:
8-/16-bit configurable Tx and Rx for each
200 MHz DDR interface
Base address and size of the accessed DRAM are configurable
GPIO.
1-10
Exynos 4412_UM 1 Product Overview
1.2.7 System Peripheral
The features of system peripheral are:
Real Time Clock
Full clock features: sec, min, hour, date, day, month, and year
32.768 kHz operation
Alarm interrupt
Time-tick interrupt
PLL
Four on-chip PLLs and APLL/MPLL/EPLL/VPLL
APLL generates ARM core and MSYS clocks
MPLL generates a system bus clock and special clocks
EPLL generates special clocks
VPLL generates clocks for video interface
Keypad
14 8 Key Matrix support
Provides internal de-bounce filter
Timer with Pulse Width Modulation
Five channel 32-bit internal timer with interrupt-based operation
Three channel 32-bit Timer with PWM
Programmable duty cycle, frequency, and polarity
Dead-zone generation
Supports external clock source
Multi-Core timer
64-bit global timer with four independent count comparators
Two 31-bit local timers
It can change interrupt interval without stopping reference tick timer DMA:
Micro-code programming based DMA
The specific instruction set provides flexibility to program DMA transfers
Supports linked list DMA function
Supports three enhanced built-in DMA with eight channels per DMA, so the total number of channels it
supports are 32
Supports one Memory-to-memory type optimized DMA and two Peripheral-to-memory type optimized
DMA
M2M DMA supports up to 16 burst and P2M DMA supports up to 8 burst
Watch Dog Timer
16-bit watch dog timer
1-11
Exynos 4412_UM 1 Product Overview
Thermal Management Unit (TMU)
Power Management
Clock-gating control for components
Various low power modes are available, such as Idle, Stop, Deep Stop, Deep Idle, and Sleep modes
Wake up sources in sleep mode are:
o External interrupts
o RTC alarm
o Tick timer
o Key interface
Wake up sources of Stop and Deep Stop mode are:
o MMC
o Touch screen interface
o System timer
o Entire wake up sources of Sleep mode
Wake up sources of Deep Idle mode are:
o 5.1 channel I2S
o Wake up source of Stop mode
1-12
Exynos 4412_UM 1 Product Overview
1.3 Conventions
1.3.1 Register RW Conventions
Symbol
R
W
RW
R/WC
Definition
Read Only
Write Only
Read and Write
Read and Write to
clear
Description
The application has permission to read the register field. Writes to read-only
fields have no effect.
The application has permission to write in the Register field.
The application has permission to read and writes in the Register field. The
application sets this field by writing 1’b1 and clears it by writing 1’b0.
The application has permission to read and write in the register field. The
application clears this field by writing 1’b1. A register write of 1'b0 has no
effect on this field.
R/WS
The application has permission to read and write in the register field. The
Read and Write to set application sets this field by writing 1’b1. A register write of 1'b0 has no
effect on this field.
1.3.2 Register Value Conventions
Expression
x
X
?
Device dependent
Pin value
Undefined bit
Undefined multiple bits
Undefined but depends on the device, or pin status
The value depends on the device
The value depends on the pin status
Description
1-13
Exynos 4412_UM 2 Memory Map
2
Memory Map
2.1 Overview
This section describes the base address of region.
Base Address
0x0000_0000
0x0200_0000
0x0202_0000
0x0300_0000
0x0302_0000
0x0303_0000
0x0381_0000
0x0400_0000
0x0500_0000
0x0600_0000
0x0700_0000
0x0800_0000
0x0C00_0000
0x0CE0_0000
0x1000_0000
0x4000_0000
0xA000_0000
Limit Address
0x0001_0000
0x0201_0000
0x0206_0000
0x0302_0000
0x0303_0000
0x0303_9000
0x0383_0000
0x0500_0000
0x0600_0000
0x0700_0000
0x0800_0000
0x0C00_0000
0x0CD0_0000
0x0D00_0000
0x1400_0000
0xA000_0000
0x0000_0000
Size
64 KB
64 KB
256 KB
128 KB
64 KB
36 KB
–
16 MB
16 MB
16 MB
16 MB
64 MB
–
–
–
1.5 GB
1.5 GB
iROM
iROM (mirror of 0x0 to 0x10000)
iRAM
Data memory or general purpose of Samsung
Reconfigurable Processor SRP.
I-cache or general purpose of SRP.
Configuration memory (write only) of SRP
AudioSS's SFR region
Bank0 of Static Read Only Memory Controller (SMC)
(16-bit only)
Bank1 of SMC
Bank2 of SMC
Bank3 of SMC
Reserved
Reserved
SFR region of Nand Flash Controller (NFCON)
SFR region
Memory of Dynamic Memory Controller (DMC)-0
Memory of DMC-1
Description
2-1
Exynos 4412_UM 2 Memory Map
2.2 SFR Base Address
This section describes the base address of SFR.
Base Address
0x1000_0000
0x1001_0000
0x1002_0000
0x1003_0000
0x1004_0000
0x1005_0000
0x1006_0000
0x1007_0000
0x100A_0000
0x100B_0000
0x100C_0000
0x1010_0000
0x1011_0000
0x1012_0000
0x1013_0000
0x1014_0000
0x1015_0000
0x1016_0000
0x1044_0000
0x1048_0000
0x1049_0000
0x1054_0000
0x1058_0000
0x1060_0000
0x1061_0000
0x106A_0000
0x106B_0000
0x106C_0000
0x106E_0000
0x1070_0000
0x1071_0000
0x1072_0000
0x1073_0000
0x1080_0000
IP
CHIPID
SYSREG
Power Management Unit (PMU)
CMU_TOP_PART
CMU_CORE_ISP_PART
Multi Core Timer (MCT)
Watch Dog Timer (WDT)
Real Time Clock (RTC)
KEYIF
HDMI_CEC
Thermal Management Unit (TMU)
SECKEY
TZPC0
TZPC1
TZPC2
TZPC3
TZPC4
TZPC5
Int_combiner
GIC_controller
GIC_distributor
AP_C2C
CP_C2C (Modem side)
DMC0
DMC1
PPMU_DMC_L
PPMU_DMC_R
PPMU_CPU
GPIO_C2C
TZASC_LR
TZASC_LW
TZASC_RR
TZASC_RW
G2D_ACP
2-2
Exynos 4412_UM 2 Memory Map
Base Address
0x1083_0000
0x1088_0000
0x1089_0000
0x108B_0000
0x10A4_0000
0x10A5_0000
0x1100_0000
0x1140_0000
0x1180_0000
0x1181_0000
0x1182_0000
0x1183_0000
0x1184_0000
0x1188_0000
0x1189_0000
0x11A2_0000
0x11A3_0000
0x11A4_0000
0x11A5_0000
0x11A6_0000
0x11C0_0000
0x11C8_0000
0x11E2_0000
0x1200_0000
0x1201_0000
0x1204_0000
0x1211_0000
0x1213_0000
0x1214_0000
0x1215_0000
0x1216_0000
0x1217_0000
0x1218_0000
0x1219_0000
0x121A_0000
0x121B_0000
0x121E_0000
IP
Security Sub System (SSS)
Coresight
Coresight
Coresight
SMMUG2D_ACP
SMMUSSS
GPIO_right
GPIO_left
FIMC0
FIMC1
FIMC2
FIMC3
JPEG
MIPI_CSI0
MIPI_CSI1
SMMUFIMC0
SMMUFIMC1
SMMUFIMC2
SMMUFIMC3
SMMUJPEG
FIMD0
MIPI_DSI0
SMMUFIMD0
FIMC_ISP
FIMC_DRC_TOP
FIMC_FD_TOP
MPWM_ISP
I2C0_ISP
I2C1_ISP
MTCADC_ISP
PWM_ISP
WDT_ISP
MCUCTL_ISP
UART_ISP
SPI0_ISP
SPI1_ISP
GIC_C_ISP
2-3
Exynos 4412_UM 2 Memory Map
Base Address
0x121F_0000
0x1226_0000
0x1227_0000
0x122A_0000
0x122B_0000
0x1239_0000
0x123A_0000
0x123B_0000
0x123C_0000
0x1248_0000
0x1249_0000
0x124A_0000
0x124B_0000
0x1250_0000
0x1251_0000
0x1252_0000
0x1253_0000
0x1254_0000
0x1255_0000
0x1256_0000
0x1257_0000
0x1258_0000
0x1259_0000
0x125B_0000
0x1268_0000
0x1269_0000
0x126C_0000
0x1281_0000
0x1284_0000
0x1285_0000
0x12A3_0000
0x12A4_0000
0x12C0_0000
0x12C1_0000
0x12D0_0000
0x12D1_0000
0x12D2_0000
IP
GIC_D_ISP
sysMMU_FIMC-ISP
sysMMU_FIMC-DRC
sysMMU_FIMC-FD
sysMMU_ISPCPU
FIMC_LITE0
FIMC_LITE1
sysMMU_FIMC-LITE0
sysMMU_FIMC-LITE1
USBDEV0
USBDEV0
USBDEV0
USBDEV0
Transport Stream Interface (TSI)
SDMMC0
SDMMC1
SDMMC2
SDMMC3
SDMMC4
MIPI_HSI
SROMC
USBHOST0
USBHOST1
USBOTG1
PDMA0
PDMA1
General ADC
Rotator
sMDMA
nsMDMA
SMMURotator
SMMUMDMA
Video Processor (VP)
Mixer
HDMI0
HDMI1
HDMI2
2-4
Exynos 4412_UM 2 Memory Map
Base Address
0x12D3_0000
0x12D4_0000
0x12D5_0000
0x12D6_0000
0x12E2_0000
0x1300_0000
0x1322_0000
0x1340_0000
0x1362_0000
0x1363_0000
0x1366_0000
0x1367_0000
0x1380_0000
0x1381_0000
0x1382_0000
0x1383_0000
0x1384_0000
0x1386_0000
0x1387_0000
0x1388_0000
0x1389_0000
0x138A_0000
0x138B_0000
0x138C_0000
0x138D_0000
0x138E_0000
0x1392_0000
0x1393_0000
0x1394_0000
0x1396_0000
0x1397_0000
0x1398_0000
0x1399_0000
0x139A_0000
0x139B_0000
0x139D_0000
IP
HDMI3
HDMI4
HDMI5
HDMI6
SMMUTV
3D Graphic Accelerator (G3D)
PPMU_3D
Multi Format Codec (MFC)
SMMUMFC_L
SMMUMFC_R
PPMU_MFC_L
PPMU_MFC_R
Universal Asynchronous Receiver And Transmitter0 (UART)
UART1
UART2
UART3
UART4
Inter-Integrated Circuit0 (I2C)
I2C1
I2C2
I2C3
I2C4
I2C5
I2C6
I2C7
I2CHDMI
Serial Peripheral Interface0 (SPI)
SPI1
SPI2
I2S1
I2S2
PCM1
PCM2
AC97
SPDIF
PWMTimer
2-5
Exynos 4412_UM 3 Chip ID
3
Chip ID
3.1 Overview
The Exynos 4412 includes a Chip ID block for the Software (SW) that sends and receives Advanced Peripheral
Bus (APB) interface signals to the bus system.
3-1
Exynos 4412_UM 3 Chip ID
3.2 Register Description
3.2.1 Register Map Summary
Base Address: 0x1000_0000
Register
PRO_ID
PACKAGE_ID
3.2.1.1 PRO_ID
Base Address: 0x1000_0000
Address = Base Address + 0x0000, Reset Value = 0xE441_2XXX
Name
Product ID
RSVD
Package
MainRev
SubRev
Bit
[31:12]
[11:10]
[9:8]
[7:4]
[3:0]
Type
R
R
R
R
R
Product ID
Reserved
Package Information
Main Revision Number
Sub Revision Number
Description Reset Value
0x4412
0x0
Exynos 4412:
0x2
0x1
0x1
Offset
0x0000
0x0004
Description
Product information (ID, package, and revision)
Package information (POP type and package)
Reset Value
0xE441_2XXX
0xXXXX_XXXX
NOTE:
PRO_ID register[31:0] depends on the e-fuse ROM value. As power on sequence is progressing, it loads the e-fuse
ROM values to the registers. It can read the loaded current e-fuse ROM values. An e-fuse ROM has main and sub
revision numbers.
3.2.1.2 PACKAGE_ID
Base Address: 0x1000_0000
Address = Base Address + 0x0004, Reset Value = 0xXXXX_XXXX
Name
Package ID
Bit
[31:0]
Type
R
Description
Package information (POP type and package)
Reset Value
0xXXXX_XXXX
NOTE:
PACKAGE_ID register[31:0] depends on the e-fuse ROM value.
3-2
Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control
4
General Purpose Input/Output (GPIO) Control
This chapter describes the General Purpose Input/Output (GPIO).
4.1 Overview
Exynos 4412 contains 304 multi-functional input/output port pins and 164 memory port pins. There are 37 general
port groups and two memory port groups. They are:
GPA0, GPA1: 14 in/out ports-3xUART with flow control, UART without flow control, and/or 2xI2C
GPB: 8 in/out ports-2xSPI and/or 2xI2C and/ or IEM
GPC0, GPC1: 10 in/out ports-2xI2S, and/or 2xPCM, and/or AC97, SPDIF, I2C, and/or SPI
GPD0, GPD1: 8 in/out ports-PWM, 2xI2C, and/ or LCD I/F, MIPI
GPM0, GPM1, GPM2, GPM3, GPM4: 35 in/out ports-CAM I/F, and/ or TS I/F, HSI, and/ or Trace I/F
GPF0, GPF1, GPF2, GPF3: 30 in/out ports-LCD I/F
GPJ0, GPJ1: 13 in/out ports-CAM I/F
GPK0, GPK1, GPK2, GPK3: 28 in/out ports-4xMMC (4-bit MMC), and/or 2xMMC (8-bit MMC)), and/or GPS
debugging I/F
GPL0, GPL1: 11 in/out ports-GPS I/F
GPL2: 8 in/out ports-GPS debugging I/F or Key pad I/F
GPX0, GPX1, GPX2, GPX3: 32 in/out ports-External wake-up, and/or Key pad I/F
NOTE:
These are in ALIVE region.
4-1
Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control
GPZ: 7 in/out ports-low Power I2S and/or PCM
GPY0, GPY1, GPY2: 16 in/out ports-Control signals of EBI (SROM, NF, One NAND)
GPY3, GPY4, GPY5, GPY6: 32 in/out memory ports-EBI (For more information about EBI configuration, refer
to Chapter 5, and 6)
MP1_0-MP1_9: 78 DRAM1 ports
NOTE:
GPIO registers does not control these ports.
MP2_0-MP2_9: 78 DRAM2 ports
NOTE:
GPIO registers does not control these ports.
Warning: When you do not use or connect port to an input pin without Pull-up/Pull-down then do not leave a
port in Input Pull-up/Pull-down disable state. It may cause unexpected state and leakage current.
Disable Pull-up/Pull-down when you use port as output function.
ETC0, ETC1, ETC6: 18 in/out ETC ports-JTAG, SLIMBUS, RESET, CLOCK
ETC7, ETC8 : 4 clock port for C2C
4-2
Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control
4.2 Features
The features of GPIO include:
4.2.1 Input/Output Description
This section includes:
General Purpose Input/Output Block Diagram
Register Description
Controls 172 External Interrupts
Controls 32 External Wake-up Interrupts
252 multi-functional input/output ports
Controls pin states in Sleep Mode except GPX0, GPX1, GPX2, and GPX3 (GPX* pins are alive-pads)
4-3
Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control
4.2.1.1 General Purpose Input/Output Block Diagram
GPIO consists of two parts,
alive-part
off-part
In Alive-part, you should supply power on sleep mode, but in off-part, it is not same. Therefore, registers in alive-part keep their values during sleep mode.
Figure 4-1 illustrates the block diagram of GPIO.
Register FileMux controlPad controlAPB BusAPB InterfaceExternal InterruptControlOff PartInterruptControllerAsync InterfaceMux controlPad controlRegister FileExternal InterruptControlAlive PartInterruptController &Wake-upcontroller
Figure 4-1 GPIO Block Diagram
4-4
Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control
4.3 Register Description
4.3.1 Registers Summary
Base Address: 0x1140_0000
Register
GPA0CON
GPA0DAT
GPA0PUD
GPA0DRV
GPA0CONPDN
GPA0PUDPDN
GPA1CON
GPA1DAT
GPA1PUD
GPA1DRV
GPA1CONPDN
GPA1PUDPDN
GPBCON
GPBDAT
GPBPUD
GPBDRV
GPBCONPDN
GPBPUDPDN
GPC0CON
GPC0DAT
GPC0PUD
GPC0DRV
GPC0CONPDN
GPC0PUDPDN
GPC1CON
GPC1DAT
GPC1PUD
GPC1DRV
GPC1CONPDN
GPC1PUDPDN
Offset
0x0000
0x0004
0x0008
0x0010
0x0014
0x0020
0x0024
0x0028
0x0030
0x0034
0x0040
0x0044
0x0048
0x0050
0x0054
0x0060
0x0064
0x0068
0x0070
0x0074
0x0080
0x0084
0x0088
0x0090
0x0094
Description
Port group GPA0 configuration register
Port group GPA0 data register
Port group GPA0 pull-up/pull-down register
Port group GPA0 power down mode configuration register
Port group GPA0 power down mode pull-up/pull-down
register
Port group GPA1 configuration register
Port group GPA1 data register
Port group GPA1 pull-up/pull-down register
Port group GPA1 power down mode configuration register
Port group GPA1 power down mode pull-up/pull-down
register
Port group GPB configuration register
Port group GPB data register
Port group GPB pull-up/pull-down register
Port group GPB power down mode configuration register
Port group GPB power down mode pull-up/pull-down
register
Port group GPC0 configuration register
Port group GPC0 data register
Port group GPC0 Pull-up/pull-down register
Port group GPC0 power down mode configuration register
Port group GPC0 power down mode pull-up/pull-down
register
Port group GPC1 configuration register
Port group GPC1 data register
Port group GPC1 pull-up/pull-down register
Port group GPC1 power down mode configuration register
Port group GPC1 power down mode pull-up/pull-down
Reset Value
0x0000_0000
0x00
0x5555
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x0555
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x5555
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x0155
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x0155
0x00_0000
0x0000
0x0000
0x000C Port group GPA0 drive strength control register
0x002C Port group GPA1 drive strength control register
0x004C Port group GPB drive strength control register
0x006C Port group GPC0 drive strength control register
0x008C Port group GPC1 drive strength control register
4-5
Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control
Register
GPD0CON
GPD0DAT
GPD0PUD
GPD0DRV
GPD0CONPDN
GPD0PUDPDN
GPD1CON
GPD1DAT
GPD1PUD
GPD1DRV
GPD1CONPDN
GPD1PUDPDN
GPF0CON
GPF0DAT
GPF0PUD
GPF0DRV
GPF0CONPDN
GPF0PUDPDN
GPF1CON
GPF1DAT
GPF1PUD
GPF1DRV
GPF1CONPDN
GPF1PUDPDN
GPF2CON
GPF2DAT
GPF2PUD
GPF2DRV
GPF2CONPDN
GPF2PUDPDN
GPF3CON
GPF3DAT
Offset
register
Description Reset Value
0x0000_0000
0x00
0x0055
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x0055
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x5555
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x5555
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x5555
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x00A0 Port group GPD0 configuration register
0x00A4 Port group GPD0 data register
0x00A8 Port group GPD0 pull-up/pull-down register
0x00AC Port group GPD0 drive strength control register
0x00B0 Port group GPD0 power down mode configuration register
0x00B4
Port group GPD0 power down mode pull-up/pull-down
register
0x00C0 Port group GPD1 configuration register
0x00C4 Port group GPD1 data register
0x00C8 Port group GPD1 Pull-up/pull-down register
0x00CC Port group GPD1 drive strength control register
0x00D0 Port group GPD1 power down mode configuration register
0x00D4
0x0180
0x0184
0x0188
0x0190
0x0194
Port group GPD1 power down mode pull-up/pull-down
register
Port group GPF0 configuration register
Port group GPF0 data register
Port group GPF0 pull-up/pull-down register
Port group GPF0 power down mode configuration register
Port group GPF0 power down mode pull-up/pull-down
register
0x018C Port group GPF0 drive strength control register
0x01A0 Port group GPF1 configuration register
0x01A4 Port group GPF1 data register
0x01A8 Port group GPF1 pull-up/pull-down register
0x01AC Port group GPF1 drive strength control register
0x01B0 Port group GPF1 power down mode configuration register
0x01B4
Port group GPF1 power down mode pull-up/pull-down
register
0x01C0 Port group GPF2 configuration register
0x01C4 Port group GPF2 data register
0x01C8 Port group GPF2 pull-up/pull-down register
0x01CC Port group GPF2 drive strength control register
0x01D0 Port group GPF2 power down mode configuration register
0x01D4
Port group GPF2 power down mode pull-up/pull-down
register
0x01E0 Port group GPF3 configuration register
0x01E4 Port group GPF3 data register
4-6
Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control
Register
GPF3PUD
GPF3DRV
GPF3CONPDN
GPF3PUDPDN
ETC1PUD
ETC1DRV
GPJ0CON
GPJ0DAT
GPJ0PUD
GPJ0DRV
GPJ0CONPDN
GPJ0PUDPDN
GPJ1CON
GPJ1DAT
GPJ1PUD
GPJ1DRV
GPJ1CONPDN
GPJ1PUDPDN
EXT_INT1_CON
EXT_INT2_CON
EXT_INT3_CON
EXT_INT4_CON
EXT_INT5_CON
EXT_INT6_CON
EXT_INT7_CON
EXT_INT13_CON
EXT_INT14_CON
EXT_INT15_CON
EXT_INT16_CON
EXT_INT21_CON
EXT_INT22_CON
EXT_INT1_FLTCON0
EXT_INT1_FLTCON1
EXT_INT2_FLTCON0
Offset Description Reset Value
0x0555
0x00_0000
0x0000
0x0000
0x0005
0x00_0000
0x0000_0000
0x00
0x5555
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x0155
0x00_0000
0x0000
0x0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x01E8 Port group GPF3 pull-up/pull-down register
0x01EC Port group GPF3 drive strength control register
0x01F0 Port group GPF3 power down mode configuration register
0x01F4
0x0228
0x0240
0x0244
0x0248
0x0250
0x0254
0x0260
0x0264
0x0268
0x0270
0x0274
0x0700
0x0704
0x0708
0x0710
0x0714
0x0718
0x0730
0x0734
0x0738
0x0740
0x0744
0x0800
0x0804
0x0808
Port group GPF3 power down mode pull-up/pull-down
register
Port group ETC1 pull-up/pull-down register
Port group GPJ0 configuration register
Port group GPJ0 data register
Port group GPJ0 pull-up/pull-down register
Port group GPJ0 power down mode configuration register
Port group GPJ0 power down mode pull-up/pull-down
register
Port group GPJ1 configuration register
Port group GPJ1 data register
Port group GPJ1 pull-up/pull-down register
Port group GPJ1 power down mode configuration register
Port group GPJ1 power down mode pull-up/pull-down
register
External interrupt EXT_INT1 configuration register
External interrupt EXT_INT2 configuration register
External interrupt EXT_INT3 configuration register
External interrupt EXT_INT5 configuration register
External interrupt EXT_INT6 configuration register
External interrupt EXT_INT7 configuration register
External interrupt EXT_INT13 configuration register
External interrupt EXT_INT14 configuration register
External interrupt EXT_INT15 configuration register
External interrupt EXT_INT21 configuration register
External interrupt EXT_INT22 configuration register
External interrupt EXT_INT1 filter configuration register 0
External interrupt EXT_INT1 filter configuration register 1
External interrupt EXT_INT2 filter configuration register 0
0x022C Port group ETC1 drive strength control register
0x024C Port group GPJ0 drive strength control register
0x026C Port group GPJ1 drive strength control register
0x070C External interrupt EXT_INT4 configuration register
0x073C External interrupt EXT_INT16 configuration register
4-7
Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control
Register
EXT_INT2_FLTCON1
EXT_INT3_FLTCON0
EXT_INT3_FLTCON1
EXT_INT4_FLTCON0
EXT_INT4_FLTCON1
EXT_INT5_FLTCON0
EXT_INT5_FLTCON1
EXT_INT6_FLTCON0
EXT_INT6_FLTCON1
EXT_INT7_FLTCON0
EXT_INT7_FLTCON1
EXT_INT13_FLTCON0
EXT_INT13_FLTCON1
EXT_INT14_FLTCON0
EXT_INT15_FLTCON0
EXT_INT15_FLTCON1
EXT_INT16_FLTCON0
EXT_INT21_FLTCON0
EXT_INT21_FLTCON1
EXT_INT22_FLTCON0
EXT_INT1_MASK
EXT_INT2_MASK
EXT_INT3_MASK
EXT_INT4_MASK
EXT_INT5_MASK
EXT_INT6_MASK
EXT_INT7_MASK
EXT_INT13_MASK
EXT_INT14_MASK
EXT_INT15_MASK
EXT_INT16_MASK
EXT_INT21_MASK
EXT_INT22_MASK
EXT_INT1_PEND
Offset
0x0810
0x0814
0x0818
0x0820
0x0824
0x0828
0x0830
0x0834
0x0860
0x0864
0x0868
0x0870
0x0874
0x0878
0x0880
0x0884
0x0888
0x0900
0x0904
0x0908
0x0910
0x0914
0x0918
0x0930
0x0934
0x0938
0x0940
0x0944
Description
External interrupt EXT_INT3 filter configuration register 0
External interrupt EXT_INT3 filter configuration register 1
External interrupt EXT_INT4 filter configuration register 0
External interrupt EXT_INT5 filter configuration register 0
External interrupt EXT_INT5 filter configuration register 1
External interrupt EXT_INT6 filter configuration register 0
External interrupt EXT_INT7 filter configuration register 0
External interrupt EXT_INT7 filter configuration register 1
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x080C External interrupt EXT_INT2 filter configuration register 1
0x081C External interrupt EXT_INT4 filter configuration register 1
0x082C External interrupt EXT_INT6 filter configuration register 1
External interrupt EXT_INT13 filter configuration register 0 0x0000_0000
External interrupt EXT_INT13 filter configuration register 1 0x0000_0000
External interrupt EXT_INT14 filter configuration register 0 0x0000_0000
External interrupt EXT_INT15 filter configuration register 0 0x0000_0000
External interrupt EXT_INT15 filter configuration register 1 0x0000_0000
External interrupt EXT_INT16 filter configuration register 0 0x0000_0000
External interrupt EXT_INT21 filter configuration register 0 0x0000_0000
External interrupt EXT_INT21 filter configuration register 1 0x0000_0000
External interrupt EXT_INT22 filter configuration register 0 0x0000_0000
External interrupt EXT_INT1 mask register
External interrupt EXT_INT2 mask register
External interrupt EXT_INT3 mask register
External interrupt EXT_INT5 mask register
External interrupt EXT_INT6 mask register
External interrupt EXT_INT7 mask register
External interrupt EXT_INT13 mask register
External interrupt EXT_INT14 mask register
External interrupt EXT_INT15 mask register
External interrupt EXT_INT21 mask register
External interrupt EXT_INT22 mask register
0x0000_00FF
0x0000_003F
0x0000_00FF
0x0000_001F
0x0000_001F
0x0000_000F
0x0000_000F
0x0000_00FF
0x0000_00FF
0x0000_00FF
0x0000_003F
0x0000_00FF
0x0000_001F
0x0000_0000
EXT_INT14_FLTCON1 0x086C External interrupt EXT_INT14 filter configuration register 1 0x0000_0000
EXT_INT16_FLTCON1 0x087C External interrupt EXT_INT16 filter configuration register 1 0x0000_0000
EXT_INT22_FLTCON1 0x088C External interrupt EXT_INT22 filter configuration register 1 0x0000_0000
0x090C External interrupt EXT_INT4 mask register
0x093C External interrupt EXT_INT16 mask register
0x0A00 External interrupt EXT_INT1 pending register
4-8
Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control
Register
EXT_INT2_PEND
EXT_INT3_PEND
EXT_INT4_PEND
EXT_INT5_PEND
EXT_INT6_PEND
EXT_INT7_PEND
EXT_INT13_PEND
EXT_INT14_PEND
EXT_INT15_PEND
EXT_INT16_PEND
EXT_INT21_PEND
EXT_INT22_PEND
EXT_INT_SERVICE
_XB
EXT_INT_SERVICE
_PEND_XB
EXT_INT_GRPFIXPRI
_XB
EXT_INT1_FIXPRI
EXT_INT2_FIXPRI
EXT_INT3_FIXPRI
EXT_INT4_FIXPRI
EXT_INT5_FIXPRI
EXT_INT6_FIXPRI
EXT_INT7_FIXPRI
EXT_INT13_FIXPRI
EXT_INT14_FIXPRI
EXT_INT15_FIXPRI
EXT_INT16_FIXPRI
EXT_INT21_FIXPRI
EXT_INT22_FIXPRI
PDNEN
Offset Description Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x00
0x0A04 External interrupt EXT_INT2 pending register
0x0A08 External interrupt EXT_INT3 pending register
0x0A0C External interrupt EXT_INT4 pending register
0x0A10 External interrupt EXT_INT5 pending register
0x0A14 External interrupt EXT_INT6 pending register
0x0A18 External interrupt EXT_INT7 pending register
0x0A30 External interrupt EXT_INT13 pending register
0x0A34 External interrupt EXT_INT14 pending register
0x0A38 External interrupt EXT_INT15 pending register
0x0A3C External interrupt EXT_INT16 pending register
0x0A40 External interrupt EXT_INT21 pending register
0x0A44 External interrupt EXT_INT22 pending register
0x0B08 Current service register
0x0B0C Current service pending register
0x0B10 External interrupt group fixed priority control register
0x0B14 External interrupt 1 fixed priority control register
0x0B18 External interrupt 2 fixed priority control register
0x0B1C External interrupt 3 fixed priority control register
0x0B20 External interrupt 4 fixed priority control register
0x0B24 External interrupt 5 fixed priority control register
0x0B28 External interrupt 6 fixed priority control register
0x0B2C External interrupt 7 fixed priority control register
0x0B44 External interrupt 13 fixed priority control register
0x0B48 External interrupt 14 fixed priority control register
0x0B4C External interrupt 15 fixed priority control register
0x0B50 External interrupt 16 fixed priority control register
0x0B54 External interrupt 21 fixed priority control register
0x0B58 External interrupt 22 fixed priority control register
0x0F80 Power down mode pad configure register
4-9
Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control
Base Address: 0x1100_0000
Register Offset
0x0040
0x0044
0x0048
0x0050
0x0054
0x0060
0x0064
0x0068
0x0070
0x0074
0x0080
0x0084
0x0088
0x0090
0x0094
Description
Port group GPK0 configuration register
Port group GPK0 data register
Port group GPK0 pull-up/pull-down register
Port group GPK0 power down mode configuration register
Port group GPK0 power down mode pull-up/pull-down
register
Port group GPK1 configuration register
Port group GPK1 data register
Port group GPK1 pull-up/pull-down register
Port group GPK1 power down mode configuration register
Port group GPK1 power down mode pull-up/pull-down
register
Port group GPK2 configuration register
Port group GPK2 data register
Port group GPK2 pull-up/pull-down register
Port group GPK2 power down mode configuration register
Port group GPK2 power down mode pull-up/pull-down
register
Reset Value
0x0000_0000
0x00
0x1555
0x00_2AAA
0x0000
0x0000
0x0000_0000
0x00
0x1555
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x1555
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x1555
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x1555
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
GPK0CON
GPK0DAT
GPK0PUD
GPK0DRV
GPK0CONPDN
GPK0PUDPDN
GPK1CON
GPK1DAT
GPK1PUD
GPK1DRV
GPK1CONPDN
GPK1PUDPDN
GPK2CON
GPK2DAT
GPK2PUD
GPK2DRV
GPK2CONPDN
GPK2PUDPDN
GPK3CON
GPK3DAT
GPK3PUD
GPK3DRV
GPK3CONPDN
GPK3PUDPDN
GPL0CON
GPL0DAT
GPL0PUD
GPL0DRV
GPL0CONPDN
GPL0PUDPDN
GPL1CON
GPL1DAT
0x004C Port group GPK0 drive strength control register
0x006C Port group GPK1 drive strength control register
0x008C Port group GPK2 drive strength control register
0x00A0 Port group GPK3 configuration register
0x00A4 Port group GPK3 data register
0x00A8 Port group GPK3 pull-up/pull-down register
0x00AC Port group GPK3 drive strength control register
0x00B0 Port group GPK3 power down mode configuration register
0x00B4
Port group GPK3 power down mode pull-up/pull-down
register
0x00C0 Port group GPL0 configuration register
0x00C4 Port group GPL0 data register
0x00C8 Port group GPL0 pull-up/pull-down register
0x00CC Port group GPL0 drive strength control register
0x00D0 Port group GPL0 power down mode configuration register
0x00D4
Port group GPL0 power down mode pull-up/pull-down
register
0x00E0 Port group GPL1 configuration register
0x00E4 Port group GPL1 data register
4-10
Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control
Register
GPL1PUD
GPL1DRV
GPL1CONPDN
GPL1PUDPDN
GPL2CON
GPL2DAT
GPL2PUD
GPL2DRV
GPL2CONPDN
GPL2PUDPDN
GPY0CON
GPY0DAT
GPY0PUD
GPY0DRV
GPY0CONPDN
GPY0PUDPDN
GPY1CON
GPY1DAT
GPY1PUD
GPY1DRV
GPY1CONPDN
GPY1PUDPDN
GPY2CON
GPY2DAT
GPY2PUD
GPY2DRV
GPY2CONPDN
GPY2PUDPDN
GPY3CON
GPY3DAT
GPY3PUD
GPY3DRV
GPY3CONPDN
Offset Description Reset Value
0x0005
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x5555
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x0FFF
0x00_0AAA
0x0000
0x0000
0x0000_0000
0x00
0x00FF
0x00_00AA
0x0000
0x0000
0x0000_0000
0x00
0x0FFF
0x00_0AAA
0x0000
0x0000
0x0000_0000
0x00
0x5555
0x00_AAAA
0x0000
0x00E8 Port group GPL1 pull-up/pull-down register
0x00EC Port group GPL1 drive strength control register
0x00F0 Port group GPL1 power down mode configuration register
0x00F4
0x0100
0x0104
0x0108
0x0110
0x0114
0x0120
0x0124
0x0128
0x0130
0x0134
0x0140
0x0144
0x0148
0x0150
0x0154
0x0160
0x0164
0x0168
0x0170
0x0174
0x0180
0x0184
0x0188
0x0190
Port group GPL1 power down mode pull-up/pull-down
register
Port group GPL2 configuration register
Port group GPL2 data register
Port group GPL2 pull-up/pull-down register
Port group GPL2 power down mode configuration register
Port group GPL2 power down mode pull-up/pull-down
register
Port group GPY0 configuration register
Port group GPY0 data register
Port group GPY0 pull-up/pull-down register
Port group GPY0 power down mode configuration register
Port group GPY0 power down mode pull-up/pull-down
register
Port group GPY1 configuration register
Port group GPY1 data register
Port group GPY1 pull-up/pull-down register
Port group GPY1 power down mode configuration register
Port group GPY1 power down mode pull-up/pull-down
register
Port group GPY2 configuration register
Port group GPY2 data register
Port group GPY2 pull-up/pull-down register
Port group GPY2 power down mode configuration register
Port group GPY2 power down mode pull-up/pull-down
register
Port group GPY3 configuration register
Port group GPY3 data register
Port group GPY3 pull-up/pull-down register
Port group GPY3 power down mode configuration register
0x010C Port group GPL2 drive strength control register
0x012C Port group GPY0 drive strength control register
0x014C Port group GPY1 drive strength control register
0x016C Port group GPY2 drive strength control register
0x018C Port group GPY3 drive strength control register
4-11
Exynos 4412_UM 4 General Purpose Input/Output (GPIO) Control
Register
GPY3PUDPDN
GPY4CON
GPY4DAT
GPY4PUD
GPY4DRV
GPY4CONPDN
GPY4PUDPDN
GPY5CON
GPY5DAT
GPY5PUD
GPY5DRV
GPY5CONPDN
GPY5PUDPDN
GPY6CON
GPY6DAT
GPY6PUD
GPY6DRV
GPY6CONPDN
GPY6PUDPDN
ETC0PUD
ETC0DRV
ETC6PUD
ETC6DRV
GPM0CON
GPM0DAT
GPM0PUD
GPM0DRV
GPM0CONPDN
GPM0PUDPDN
GPM1CON
GPM1DAT
GPM1PUD
GPM1DRV
Offset
0x0194
Description
Port group GPY3 power down mode pull-up/pull-down
register
Reset Value
0x0000
0x0000_0000
0x00
0x5555
0x00_AAAA
0x0000
0x0000
0x0000_0000
0x00
0x5555
0x00_AAAA
0x0000
0x0000
0x0000_0000
0x00
0x5555
0x00_AAAA
0x0000
0x0000
0x0400
0x00_0000
0xC000
0x00_0000
0x0000_0000
0x00
0x5555
0x00_0000
0x0000
0x0000
0x0000_0000
0x00
0x1555
0x00_0000
0x01A0 Port group GPY4 configuration register
0x01A4 Port group GPY4 data register
0x01A8 Port group GPY4 pull-up/pull-down register
0x01AC Port group GPY4 drive strength control register
0x01B0 Port group GPY4 power down mode configuration register
0x01B4
Port group GPY4 power down mode pull-up/pull-down
register
0x01C0 Port group GPY5 configuration register
0x01C4 Port group GPY5 data register
0x01C8 Port group GPY5 pull-up/pull-down register
0x01CC Port group GPY5 drive strength control register
0x01D0 Port group GPY5 power down mode configuration register
0x01D4
Port group GPY5 power down mode pull-up/pull-down
register
0x01E0 Port group GPY6 configuration register
0x01E4 Port group GPY6 data register
0x01E8 Port group GPY6 pull-up/pull-down register
0x01EC Port group GPY6 drive strength control register
0x01F0 Port group GPY6 power down mode configuration register
0x01F4
0x0208
0x0228
0x0260
0x0264
0x0268
0x0270
0x0274
0x0280
0x0284
0x0288
Port group GPY6 power down mode pull-up/pull-down
register
Port group ETC0 pull-up/pull-down register
Port group ETC6 pull-up/pull-down register
Port group GPM0 configuration register
Port group GPM0 data register
Port group GPM0 pull-up/pull-down register
Port group GPM0 power down mode configuration register
Port group GPM0 power down mode pull-up/pull-down
register
Port group GPM1 configuration register
Port group GPM1 data register
Port group GPM1 pull-up/pull-down register
0x020C Port group ETC0 drive strength control register
0x022C Port group ETC6 drive strength control register
0x026C Port group GPM0 drive strength control register
0x028C Port group GPM1 drive strength control register
4-12
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