2023年12月30日发(作者：炒股笔记本电脑排行榜)

8Gb: x4, x8, x16 DDR4 SDRAMFeaturesDDR4 SDRAMMT40A2G4MT40A1G8MT40A512M16Features•••••VDD = VDDQ = 1.2V ±60mVVPP = 2.5V, –125mV, +250mVOn-die, internal, adjustable VREFDQ generation1.2V pseudo open-drain I/ORefresh time of 8192-cycle at TC temperature range:–64ms at -40°C to 85°C–32ms at >85°C to 95°C–16ms at >95°C to 105°C16 internal banks (x4, x8): 4 groups of 4 banks each8 internal banks (x16): 2 groups of 4 banks each8n-bit prefetch architectureProgrammable data strobe preamblesData strobe preamble trainingCommand/Address latency (CAL)Multipurpose register READ and WRITE capabilityWrite levelingSelf refresh modeLow-power auto self refresh (LPASR)Temperature controlled refresh (TCR)Fine granularity refreshSelf refresh abortMaximum power savingOutput driver calibrationNominal, park, and dynamic on-die termination(ODT)Data bus inversion (DBI) for data busCommand/Address (CA) parityDatabus write cyclic redundancy check (CRC)Per-DRAM addressabilityConnectivity testJEDEC JESD-79-4 compliantsPPR and hPPR capabilityOptions1•Configuration–2 Gig x 4–1 Gig x 8–512 Meg x 16•78-ball FBGA package (Pb-free) – x4,x8–9mm x 13.2mm – Rev. A–8mm x 12mm – Rev. B, D, G–7.5mm x 11mm – Rev. E, H, J•96-ball FBGA package (Pb-free) – x16–9mm x 14mm – Rev. A–8mm x 14mm – Rev. B–7.5mm x 13.5mm – Rev. D, E, H–7.5mm x 13mm – Rev. J•Timing – cycle time–0.625ns @ CL = 22 (DDR4-3200)–0.682ns @ CL = 21 (DDR4-2933)–0.750ns @ CL = 19 (DDR4-2666)–0.750ns @ CL = 18 (DDR4-2666)–0.833ns @ CL = 17 (DDR4-2400)–0.833ns @ CL = 16 (DDR4-2400)–0.937ns @ CL = 15 (DDR4-2133)–1.071ns @ CL = 13 (DDR4-1866)•Operating temperature–Commercial (0° ื TC ื 95°C)–Industrial (–40° ื TC ื 95°C)–Automotive (–40° ื TC ื 105°C)•RevisionNote:Marking2G41G8512M16PMWESAHAJYLYTB-062E-068-075-075E-083-083E-093E-107ENoneITAT:A, :B, :D, :E,:G, :H, :J••••••••••••••••••••••• all options listed can be combined todefine an offered product. Use the partcatalog search on available 1: Key Timing ParametersSpeed Grade1-062Y-062E-068Data Rate (MT/s)32Target CL-nRCD-nRP22-22-2222-22-2221-21-21tAA (ns)tRCD (ns)tRP (ns)13.75 (13.32)13.7514.32 (13.75)13.75 (13.32)13.7514.32 (13.75)13.75 (13.32)13.7514.32 (13.75)

8Gb: x4, x8, x16 DDR4 SDRAMFeaturesTable 1: Key Timing Parameters (Continued)Speed Grade1-075E-075-083E-083-093E-093-107ENote:Data Rate (MT/s)2666266624331866Target CL-nRCD-nRP18-18-1819-19-1916-16-1617-17-1715-15-1516-16-1613-13-13tAA (ns)tRCD (ns)tRP (ns)13.5014.25 (13.75)13.3214.16 (13.75)14.06 (13.50)15.0013.92 (13.50)13.5014.25 (13.75)13.3214.16 (13.75)14.06 (13.50)15.0013.92 (13.50)13.5014.25 (13.75)13.3214.16 (13.75)14.06 (13.50)15.0013.92 (13.50) to the Speed Bin Tables for additional 2: AddressingParameterNumber of bank groupsBank group addressBank count per groupBank address in bank groupRow addressingColumn addressingPage size1Note:2048 Meg x 44BG[1:0]4BA[1:0]128K (A[16:0])1K (A[9:0])512B1024 Meg x 84BG[1:0]4BA[1:0]64K (A[15:0])1K (A[9:0])1KB512 Meg x 162BG04BA[1:0]64K (A[15:0])1K (A[9:0]) size is per bank, calculated as follows:Page size = 2COLBITS × ORG/8, where COLBIT = the number of column address bits and ORG = the number ofDQ bits.

8Gb: x4, x8, x16 DDR4 SDRAMFeaturesFigure 1: Order Part Number ExampleExample Part Number: MT40A1G8WE-083:D-MT40AConfigurationPackageSpeed:Revision{Configuration2 Gig x 41 Gig x 8512 Meg x 16Package78-ball 9.0mm x 13.2mm FBGA78-ball 8.0mm x 12.0mm FBGA78-ball 7.5mm x 11.0mm FBGA96-ball 9.0mm x 14.0mm FBGA96-ball 8.0mm x 14.0mm FBGA96-ball 7.5mm x 13.5mm FBGA96-ball 7.5mm x 13.0mm FBGA2G81G8512M16 MarkPMWESAHAJYLYTBSpeedGrade-107E-093E-083E-083-075E-075-068-062ECycle Time, CAS LatencytCK = 1.071ns, CL = 13tCK = 0.937ns, CL = 15tCK = 0.833ns, CL = 16tCK = 0.833ns, CL = 17tCK = 0.750ns, CL = 18tCK = 0.750ns, CL = 19tCK = 0.682ns, CL = 21tCK = 0.625ns, CL = 22Case TemperatureCommercialIndustrialAutomotive MarkNoneITATDie Revision:A, :B, :D, :G, :E, :H, :J

8Gb: x4, x8, x16 DDR4 SDRAMImportant Notes and WarningsImportant Notes and WarningsMicron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,including without limitation specifications and product descriptions. This document supersedes and replaces allinformation supplied prior to the publication hereof. You may not rely on any information set forth in this docu-ment if you obtain the product described herein from any unauthorized distributor or other source not authorizedby tive Applications. Products are not designed or intended for use in automotive applications unless specifi-cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim ofproduct liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micronproducts are not designed or intended for use in automotive applications unless specifically designated by Micronas automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damageresulting from any use of non-automotive-grade products in automotive al Applications. Products are not authorized for use in applications in which failure of the Micron compo-nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-mental damage by incorporating safety design measures into customer's applications to ensure that failure of theMicron component will not result in such harms. Should customer or distributor purchase, use, or sell any Microncomponent for any critical application, customer and distributor shall indemnify and hold harmless Micron andits subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim ofproduct liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of theMicron er Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINEWHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, ORPRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are includedin customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-vironmental damages will result from failure of any semiconductor d Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequentialdamages (including without limitation lost profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not such damages are based on tort, warranty,breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's dulyauthorized l Notes and DescriptionDescriptionThe DDR4 SDRAM is a high-speed dynamic random-access memory internally config-ured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the

8Gb: x4, x8, x16 DDR4 SDRAMGeneral Notes and Descriptionx4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to ach-ieve high-speed operation. The 8n-prefetch architecture is combined with an interfacedesigned to transfer two data words per clock cycle at the I/O pins.A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bitwide, four-clock data transfer at the internal DRAM core and two corresponding n-bitwide, one-half-clock-cycle data transfers at the I/O rial TemperatureAn industrial temperature (IT) device option requires that the case temperature not ex-ceed below –40°C or above 95°C. JEDEC specifications require the refresh rate to doublewhen TC exceeds 85°C; this also requires use of the high-temperature self refresh onally, ODT resistance and the input/output impedance must be derated whenoperating outside of the commercial temperature range, when TC is between –40°C and0°tive TemperatureThe automotive temperature (AT) device option requires that the case temperature notexceed below –40°C or above 105°C. The specifications require the refresh rate to 2Xwhen TC exceeds 85°C; 4X when TC exceeds 95°C. Additionally, ODT resistance and theinput/output impedance must be derated when operating temperature Tc <0°l Notes•The functionality and the timing specifications discussed in this data sheet are for theDLL enable mode of operation (normal operation), unless specifically stated other-wise.•Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQterm is to be interpreted as any and all DQ collectively, unless specifically stated oth-erwise.•The terms "_t" and "_c" are used to represent the true and complement of a differen-tial signal pair. These terms replace the previously used notation of "#" and/or over-bar characters. For example, differential data strobe pair DQS, DQS# is now referredto as DQS_t, DQS_c.•The term "_n" is used to represent a signal that is active LOW and replaces the previ-ously used "#" and/or overbar characters. For example: CS# is now referred to asCS_n.•The terms "DQS" and "CK" found throughout the data sheet are to be interpreted asDQS_t, DQS_c and CK_t, CK_c respectively, unless specifically stated otherwise.•Complete functionality may be described throughout the entire document; any pageor diagram may have been simplified to convey a topic and may not be inclusive of allrequirements.•Any specific requirement takes precedence over a general statement.•Any functionality not specifically stated here within is considered undefined, illegal,and not supported, and can result in unknown operation.•Addressing is denoted as BG[n] for bank group, BA[n] for bank address, and A[n] forrow/col address.•The NOP command is not allowed, except when exiting maximum power savingsmode or when entering gear-down mode, and only a DES command should be used.

8Gb: x4, x8, x16 DDR4 SDRAMGeneral Notes and Description•Not all features described within this document may be available on the Rev. A (first)version.•Not all specifications listed are finalized industry standards; best conservative esti-mates have been provided when an industry standard has not been finalized.•Although it is implied throughout the specification, the DRAM must be used after VDDhas reached the stable power-on level, which is achieved by toggling CKE at least onceevery 8192 ×

tREFI. However, in the event CKE is fixed HIGH, toggling CS_n at leastonce every 8192 ×

tREFI is an acceptable alternative. Placing the DRAM into self re-fresh mode also alleviates the need to toggle CKE.•Not all features designated in the data sheet may be supported by earlier die revisionsdue to late definition by JEDEC.•A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to beused, use the lower byte for data transfers and terminate the upper byte as noted:–––––Connect UDQS_t to VDDQ or VSS/ VSSQ via a resistor in the 200വ t UDQS_c to the opposite rail via a resistor in the same 200വ t UDM to VDDQ via a large (10,000വ) pull-up t UDBI to VDDQ via a large (10,000വ) pull-up t DQ [15:8] individually to VDDQ via a large (10,000വ) resistors, or float DQ[15:8] .Definitions of the Device-Pin Signal Level••••HIGH: A device pin is driving the logic 1 : A device pin is driving the logic 0 -Z: A device pin is : A device pin terminates with the ODT setting, which could be terminating or tri-state depending on the mode register tions of the Bus Signal Level•HIGH: One device on the bus is HIGH, and all other devices on the bus are either ODTor High-Z. The voltage level on the bus is nominally VDDQ.•LOW: One device on the bus is LOW, and all other devices on the bus are either ODTor High-Z. The voltage level on the bus is nominally VOL(DC) if ODT was enabled, orVSSQ if High-Z.•High-Z: All devices on the bus are High-Z. The voltage level on the bus is undefined asthe bus is floating.•ODT: At least one device on the bus is ODT, and all others are High-Z. The voltage lev-el on the bus is nominally VDDQ.•The specification requires 8,192 refresh commands within 64ms between 0 oC and 85oC. This allows for a

tREFI of 7.8125μs (the use of "7.8μs" is truncated from 7.8125μs).The specification also requires 8,192 refresh commands within 32ms between 85 oCand 95 oC. This allows for a

tREFI of 3.90625μs (the use of "3.9μs" is truncated from3.90625μs).

8Gb: x4, x8, x16 DDR4 SDRAMFunctional Block DiagramsFunctional Block DiagramsDDR4 SDRAM is a high-speed, CMOS dynamic random access memory. It is internallyconfigured as an 16-bank (4-banks per Bank Group) 2: 2 Gig x 4 Functional Block Diagram2'7=4