2024年1月12日发(作者：)

SI4463引脚解释

PIN

PIN Name I/O

1

SDN

I

I/0 Description 意思

Shutdown Input Pin.0–VDD V digital input. SDN should be = 0

关闭输入Pin.0-VDD V数字输入。SDN应该在所有模式除了关in all modes except Shutdown SDN = 1, the chip will

机模式= 0。SDN = 1时,芯片将被完全关闭,theregisters的内容be completely shut down, and the contents of theregisters will

将丢失。

be lost.

2

RXp

I

Differential RF Input Pins of the application

微分射频低噪声放大器的输入插脚。看到应用程序例如匹配网络

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3

4

RXn

TX

I

O

schematic for example matching network.

示意图。

Transmit Output PA output is an open-drain connection,

传输输出接脚。巴勒斯坦权力机构的输出是一个排水明沟连接,so the L-C match must supply VDD (+3.3 VDC nominal) to this

所以L-C匹配必须提供VDD这个销(+ 3.3 VDC名义)

pin.

5

6

NC

VDD

VDD

No Connect. Not connected internally to any circuitry.

不联系了。内部没有连接到任何电路。

+1.8 to +3.6 V Supply Voltage Input to Internal

+ 1.8 + 3.6 V电源电压输入内部监管机构。推荐的VDD + 3.0recommended VDD supply voltage is +3.0 V.

V电源电压。

7

TXRAMP

O

Programmable Bias Output with Ramp Capability for External FET

可编程的偏见与斜坡输出能力外部场效应晶体管。见参考设计。

reference design.

8

VDD

VDD

+1.8 to +3.6 V Supply Voltage Input to Internal

+ 1.8 + 3.6 V电源电压输入内部监管机构。推荐的VDD + 3.0recommended VDD supply voltage is +3.0 V.

V电源电压。

通用数字I / O。可以通过配置寄存器来执行各种功能,包括:微控制器的时钟输出,FIFO地位,穷,唤醒定时器,低电池检测,TRSW

AntDiversity控制等。

9

10

GPIO0

GPIO1

I/O

I/O

General Purpose Digital I/ be configured through the

registers to perform various functions

including:Microcontroller Clock Output, FIFO status, POR,

Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control,

etc.

11

nIRQ

O

General Microcontroller Interrupt Status the

一般的单片机中断状态输出。当Si4463/61展品中的任何一个中单片机可以确定中断的状态通过阅读中Si4463/61 exhibits any one of the interrupt events, the nIRQ

断事件,nIRQ销将低= 0。不需要外部电阻上拉,但它可能是可取的,如果多个中断线pin will be set low = 0. The Microcontroller can then determine

断状态。the state of the interrupt by reading the interrupt status.

路连接。

No external resistor pull-up is required, but it may be

desirable if multiple interrupt lines are connected.

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12

SCLK

I

Serial Clock Input.0–VDD V digital input. This pin provides

串行时钟Input.0-VDD V数字输入。这个销提供的串行数据时钟the serial data clock function for the 4-line serial data bus.

功能4线串行数据总线。数据定时到Si4463/61在积极的边缘过Data is clocked into the Si4463/61 on positive edge

transitions.

渡。

13

SDO

O

提供了一个连续的回读功能内部控制寄存器。

0–VDD V Digital es a serial readback function

0-VDD V数字输出。of the internal control registers.

14

SDI

I

Serial Data Input.0–VDD V digital input. This pin provides

串行数据Input.0-VDD V数字输入。这个销提供的串行数据流4the serial data stream for the 4-line serial data bus.

15

nSEL

I

线串行数据总线。

这个销提供的选择/启用Serial Interface Select Input.0–VDD V digital input. This pin

串行接口选择Input.0-VDD V数字输入。provides the Select/Enable function for the4-line serial data

函数the4-line串行数据总线。

bus.

16

XOUT

O

Crystal Oscillator t to an external 25.6 to 32

晶体振荡器的输出。连接到外部32 25.6 MHz水晶,或离开浮动MHz crystal, or leave floating when driving with an external

与外部源鑫开车时。

source on XIN.

17

XIN

I

Crystal Oscillator t to an external 25.6 to 32 MHz

晶体振荡器的输入。连接到外部32 25.6 MHz水晶,或连接到一crystal, or connect to an external source. If using an external

个外部来源。如果使用外部源或TCXO没有晶体,然后500 - 90source or TCXO with no crystal, then 500–900 mV amplitude is

0 mV振幅是必需的。不需要直流偏压,但是,如果使用,应该设置required. No dc bias is required, but, if used, it should be

为500 mV。

set to 500 mV.

18

19 G

GND

PIO2

GND

I/O

Connect to PCB ground.

General Purpose Digital I/ be configured through the

连接到印刷电路板。

通用数字I / O。可以通过配置寄存器来执行各种功能,包括微控

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20

GPIO3

I/O

registers to perform various functions, including

Low Battery Detect, TRSW, AntDiversity control, etc

制器的时钟输出、FIFO地位,穷,唤醒定时器,低电池检测,TRSW

Microcontroller Clock Output, FIFO status, POR, Wake-Up timer,

AntDiversity控制等。

PKG PADDLE_GND

GND The exposed metal paddle on the bottom of the Si446x supplies

裸露的金属桨的底部Si446x供应RF电路和地面(s)对整个芯片。the RF and circuit ground(s) for the entire chip. It is very

是非常重要的,一个好的焊料连接之间的接触金属桨和Si446x背important that a good solder connection is made between this

后的PCB的地平面

exposed metal paddle and the ground plane of the PCB underlying

the Si446x

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